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| author | Leon Alrae | 2015-04-21 17:06:28 +0200 |
|---|---|---|
| committer | Leon Alrae | 2015-06-11 11:13:28 +0200 |
| commit | 7c979afd11b09a16634699dd6344e3ba10c9677e (patch) | |
| tree | 2175a47d3d9f5a95406887a1b0e17c3c5c00b9d6 /tests/qapi-schema/data-array-empty.err | |
| parent | target-mips: move group of functions above gen_load_fpr32() (diff) | |
| download | qemu-7c979afd11b09a16634699dd6344e3ba10c9677e.tar.gz qemu-7c979afd11b09a16634699dd6344e3ba10c9677e.tar.xz qemu-7c979afd11b09a16634699dd6344e3ba10c9677e.zip | |
target-mips: add Config5.FRE support allowing Status.FR=0 emulation
This relatively small architectural feature adds the following:
FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
available.
Config5.FRE: When enabled all single-precision FP arithmetic instructions,
LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions
exception.
Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.
Enable the feature in MIPS64R6-generic CPU.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'tests/qapi-schema/data-array-empty.err')
0 files changed, 0 insertions, 0 deletions