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| author | Peter Maydell | 2015-08-13 12:26:22 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-08-13 12:26:22 +0200 |
| commit | a007b1f85813ef6450ad3e761e46c189e3f40e04 (patch) | |
| tree | 4aaba13964ee90785426e10c067e95a015d9fb48 /tests/qapi-schema/data-array-empty.json | |
| parent | target-arm: Add AArch32 banked register access to secure physical timer (diff) | |
| download | qemu-a007b1f85813ef6450ad3e761e46c189e3f40e04.tar.gz qemu-a007b1f85813ef6450ad3e761e46c189e3f40e04.tar.xz qemu-a007b1f85813ef6450ad3e761e46c189e3f40e04.zip | |
hw/arm/virt: Wire up secure timer interrupt
Wire up the secure timer interrupt. Since we've defined
that the plain old physical timer is the NS timer, we can
drop the now-out-of-date comment about QEMU not having TZ.
Use a data-driven loop to wire up the timer interrupts, since
we now have four of them and the code is the same for each.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1437047249-2357-4-git-send-email-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'tests/qapi-schema/data-array-empty.json')
0 files changed, 0 insertions, 0 deletions