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| author | Peter Maydell | 2015-08-25 16:45:09 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-08-25 17:18:33 +0200 |
| commit | d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d (patch) | |
| tree | 636b3f38b921da191b90f223c3513ae9c4db8551 /tests/qapi-schema/data-array-empty.json | |
| parent | target-arm: Implement AArch32 ATS1H* operations (diff) | |
| download | qemu-d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d.tar.gz qemu-d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d.tar.xz qemu-d7a74a9d4a68e27b3a8ceda17bb95cb0a23d8e4d.zip | |
cputlb: Add functions for flushing TLB for a single MMU index
Guest CPU TLB maintenance operations may be sufficiently
specialized to only need to flush TLB entries corresponding
to a particular MMU index. Implement cputlb functions for
this, to avoid the inefficiency of flushing TLB entries
which we don't need to.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1439548879-1972-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'tests/qapi-schema/data-array-empty.json')
0 files changed, 0 insertions, 0 deletions