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| author | Robert Hoo | 2018-07-05 11:09:54 +0200 |
|---|---|---|
| committer | Eduardo Habkost | 2018-08-16 18:43:01 +0200 |
| commit | 8c80c99fcceabd0708a5a83f08577e778c9419f5 (patch) | |
| tree | 19cddca7714a043daa216ad5dd0cc8f5754b08a3 /tests/qapi-schema/enum-missing-data.json | |
| parent | docs: add guidance on configuring CPU models for x86 (diff) | |
| download | qemu-8c80c99fcceabd0708a5a83f08577e778c9419f5.tar.gz qemu-8c80c99fcceabd0708a5a83f08577e778c9419f5.tar.xz qemu-8c80c99fcceabd0708a5a83f08577e778c9419f5.zip | |
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'tests/qapi-schema/enum-missing-data.json')
0 files changed, 0 insertions, 0 deletions