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| author | Max Filippov | 2020-03-14 19:13:53 +0100 |
|---|---|---|
| committer | Max Filippov | 2020-08-21 21:48:15 +0200 |
| commit | f8c613701637ebfbf75570153715af3ac7aeca9d (patch) | |
| tree | 2daf1e3b5bd4aa9c65a12b58eb98cdc1b575e3ab /tests/tcg/xtensa/macros.inc | |
| parent | target/xtensa: add DFPU registers and opcodes (diff) | |
| download | qemu-f8c613701637ebfbf75570153715af3ac7aeca9d.tar.gz qemu-f8c613701637ebfbf75570153715af3ac7aeca9d.tar.xz qemu-f8c613701637ebfbf75570153715af3ac7aeca9d.zip | |
target/xtensa: implement FPU division and square root
This does not implement all opcodes related to div/sqrt as specified in
the xtensa ISA, partly because the official specification is not
complete and partly because precise implementation is unnecessarily
complex. Instead instructions specific to the div/sqrt sequences are
implemented differently, most of them as nops, but the results of
div/sqrt sequences is preserved.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tests/tcg/xtensa/macros.inc')
0 files changed, 0 insertions, 0 deletions