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authorDavid Hildenbrand2021-01-11 17:38:44 +0100
committerCornelia Huck2021-01-21 11:19:45 +0100
commitd944293d9ab0b8338fbc681e6e5d8ac7829a702f (patch)
tree023e7cdc2d13a4a3e947330a29293de1a3a1a9ee /tests/tcg
parents390x/tcg: Don't ignore content in r0 when not specified via "b" or "x" (diff)
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tests/tcg/s390x: Fix EXRL tests
The current EXRL tests crash on real machines: we must not use r0 as a base register for trt/trtr, otherwise the content gets ignored. Also, we must not use r0 for exrl, otherwise it gets ignored. Let's use the "a" constraint so we get a general purpose register != r0. For op2, we can simply specify a memory operand directly via "Q" (Memory reference without index register and with short displacement). Fixes: ad8c851d2e77 ("target/s390x: add EX support for TRT and TRTR") Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210111163845.18148-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'tests/tcg')
-rw-r--r--tests/tcg/s390x/exrl-trt.c8
-rw-r--r--tests/tcg/s390x/exrl-trtr.c8
2 files changed, 8 insertions, 8 deletions
diff --git a/tests/tcg/s390x/exrl-trt.c b/tests/tcg/s390x/exrl-trt.c
index 3c5323aecb..16711a3181 100644
--- a/tests/tcg/s390x/exrl-trt.c
+++ b/tests/tcg/s390x/exrl-trt.c
@@ -19,7 +19,7 @@ int main(void)
}
asm volatile(
" j 2f\n"
- "1: trt 0(1,%[op1]),0(%[op2])\n"
+ "1: trt 0(1,%[op1]),%[op2]\n"
"2: exrl %[op1_len],1b\n"
" lgr %[r1],%%r1\n"
" lgr %[r2],%%r2\n"
@@ -27,9 +27,9 @@ int main(void)
: [r1] "+r" (r1),
[r2] "+r" (r2),
[cc] "=r" (cc)
- : [op1] "r" (&op1),
- [op1_len] "r" (5),
- [op2] "r" (&op2)
+ : [op1] "a" (&op1),
+ [op1_len] "a" (5),
+ [op2] "Q" (op2)
: "r1", "r2", "cc");
cc = (cc >> 28) & 3;
if (cc != 2) {
diff --git a/tests/tcg/s390x/exrl-trtr.c b/tests/tcg/s390x/exrl-trtr.c
index c33153ad7e..5f30cda6bd 100644
--- a/tests/tcg/s390x/exrl-trtr.c
+++ b/tests/tcg/s390x/exrl-trtr.c
@@ -19,7 +19,7 @@ int main(void)
}
asm volatile(
" j 2f\n"
- "1: trtr 3(1,%[op1]),0(%[op2])\n"
+ "1: trtr 3(1,%[op1]),%[op2]\n"
"2: exrl %[op1_len],1b\n"
" lgr %[r1],%%r1\n"
" lgr %[r2],%%r2\n"
@@ -27,9 +27,9 @@ int main(void)
: [r1] "+r" (r1),
[r2] "+r" (r2),
[cc] "=r" (cc)
- : [op1] "r" (&op1),
- [op1_len] "r" (3),
- [op2] "r" (&op2)
+ : [op1] "a" (&op1),
+ [op1_len] "a" (3),
+ [op2] "Q" (op2)
: "r1", "r2", "cc");
cc = (cc >> 28) & 3;
if (cc != 1) {