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| author | Richard Henderson | 2020-10-16 23:07:53 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-20 17:12:00 +0200 |
| commit | 3ab6e68cd035de244d9bf999900349a69939ad41 (patch) | |
| tree | 8e46f33644cf8b694277a2993f01c10fd7040fe5 /tests | |
| parent | hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs (diff) | |
| download | qemu-3ab6e68cd035de244d9bf999900349a69939ad41.tar.gz qemu-3ab6e68cd035de244d9bf999900349a69939ad41.tar.xz qemu-3ab6e68cd035de244d9bf999900349a69939ad41.zip | |
accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
On ARM, the Top Byte Ignore feature means that only 56 bits of
the address are significant in the virtual address. We are
required to give the entire 64-bit address to FAR_ELx on fault,
which means that we do not "clean" the top byte early in TCG.
This new interface allows us to flush all 256 possible aliases
for a given page, currently missed by tlb_flush_page*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201016210754.818257-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions