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| author | Hao Wu | 2022-07-14 20:28:31 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-07-18 14:20:14 +0200 |
| commit | 4a84e85413acaad9e84b64786e44e190080d78a6 (patch) | |
| tree | b00ee7a758880526461d79c168a121a89b036fd0 /tests | |
| parent | target/arm: Honour VTCR_EL2 bits in Secure EL2 (diff) | |
| download | qemu-4a84e85413acaad9e84b64786e44e190080d78a6.tar.gz qemu-4a84e85413acaad9e84b64786e44e190080d78a6.tar.xz qemu-4a84e85413acaad9e84b64786e44e190080d78a6.zip | |
hw/adc: Fix CONV bit in NPCM7XX ADC CON register
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture<venture@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220714182836.89602-4-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/qtest/npcm7xx_adc-test.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c index 3fa6d9ece0..8048044d28 100644 --- a/tests/qtest/npcm7xx_adc-test.c +++ b/tests/qtest/npcm7xx_adc-test.c @@ -50,7 +50,7 @@ #define CON_INT BIT(18) #define CON_EN BIT(17) #define CON_RST BIT(16) -#define CON_CONV BIT(14) +#define CON_CONV BIT(13) #define CON_DIV(rv) extract32(rv, 1, 8) #define FST_RDST BIT(1) |