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| author | Max Filippov | 2022-04-24 17:33:16 +0200 |
|---|---|---|
| committer | Max Filippov | 2022-05-07 00:27:40 +0200 |
| commit | 8164f14bb98dce986b755af4b3dfee3eb99c95a1 (patch) | |
| tree | e9d62c489142251f203cbe16780b1c061c2aeb96 /tests | |
| parent | tests/tcg/xtensa: fix build for cores without windowed registers (diff) | |
| download | qemu-8164f14bb98dce986b755af4b3dfee3eb99c95a1.tar.gz qemu-8164f14bb98dce986b755af4b3dfee3eb99c95a1.tar.xz qemu-8164f14bb98dce986b755af4b3dfee3eb99c95a1.zip | |
tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent
tests that expect to raise an exception. Restore vecbase SR to its
reset value after the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/tcg/xtensa/test_sr.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index b1a91a0637..34441c7aff 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -221,6 +221,8 @@ test_sr_mask /*scompare1*/12, 0, 0 #if XCHAL_HAVE_VECBASE test_sr vecbase, 1 +movi a2, XCHAL_VECBASE_RESET_VADDR +wsr a2, vecbase #else test_sr_mask /*vecbase*/231, 0, 0 #endif |