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| author | Song Gao | 2022-07-16 10:54:23 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-07-19 18:23:58 +0200 |
| commit | fa50579a57abd271109117936c6886d2d1e3d9af (patch) | |
| tree | e058212f2ab3113ab41c82feda7ae651b5af696b /tests | |
| parent | tests/tcg/loongarch64: Add clo related instructions test (diff) | |
| download | qemu-fa50579a57abd271109117936c6886d2d1e3d9af.tar.gz qemu-fa50579a57abd271109117936c6886d2d1e3d9af.tar.xz qemu-fa50579a57abd271109117936c6886d2d1e3d9af.zip | |
tests/tcg/loongarch64: Add div and mod related instructions test
This includes:
- DIV.{W[U]/D[U]}
- MOD.{W[U]/D[U]}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20220716085426.3098060-6-gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/tcg/loongarch64/Makefile.target | 1 | ||||
| -rw-r--r-- | tests/tcg/loongarch64/test_div.c | 54 |
2 files changed, 55 insertions, 0 deletions
diff --git a/tests/tcg/loongarch64/Makefile.target b/tests/tcg/loongarch64/Makefile.target index c0bd8b9b86..24d6bb11e9 100644 --- a/tests/tcg/loongarch64/Makefile.target +++ b/tests/tcg/loongarch64/Makefile.target @@ -11,5 +11,6 @@ VPATH += $(LOONGARCH64_SRC) LDFLAGS+=-lm LOONGARCH64_TESTS = test_bit +LOONGARCH64_TESTS += test_div TESTS += $(LOONGARCH64_TESTS) diff --git a/tests/tcg/loongarch64/test_div.c b/tests/tcg/loongarch64/test_div.c new file mode 100644 index 0000000000..6c31fe97ae --- /dev/null +++ b/tests/tcg/loongarch64/test_div.c @@ -0,0 +1,54 @@ +#include <assert.h> +#include <inttypes.h> +#include <stdio.h> + +#define TEST_DIV(N, M) \ +static void test_div_ ##N(uint ## M ## _t rj, \ + uint ## M ## _t rk, \ + uint64_t rm) \ +{ \ + uint64_t rd = 0; \ + \ + asm volatile("div."#N" %0,%1,%2\n\t" \ + : "=r"(rd) \ + : "r"(rj), "r"(rk) \ + : ); \ + assert(rd == rm); \ +} + +#define TEST_MOD(N, M) \ +static void test_mod_ ##N(uint ## M ## _t rj, \ + uint ## M ## _t rk, \ + uint64_t rm) \ +{ \ + uint64_t rd = 0; \ + \ + asm volatile("mod."#N" %0,%1,%2\n\t" \ + : "=r"(rd) \ + : "r"(rj), "r"(rk) \ + : ); \ + assert(rd == rm); \ +} + +TEST_DIV(w, 32) +TEST_DIV(wu, 32) +TEST_DIV(d, 64) +TEST_DIV(du, 64) +TEST_MOD(w, 32) +TEST_MOD(wu, 32) +TEST_MOD(d, 64) +TEST_MOD(du, 64) + +int main(void) +{ + test_div_w(0xffaced97, 0xc36abcde, 0x0); + test_div_wu(0xffaced97, 0xc36abcde, 0x1); + test_div_d(0xffaced973582005f, 0xef56832a358b, 0xffffffffffffffa8); + test_div_du(0xffaced973582005f, 0xef56832a358b, 0x11179); + test_mod_w(0x7cf18c32, 0xa04da650, 0x1d3f3282); + test_mod_wu(0x7cf18c32, 0xc04da650, 0x7cf18c32); + test_mod_d(0x7cf18c3200000000, 0xa04da65000000000, 0x1d3f328200000000); + test_mod_du(0x7cf18c3200000000, 0xc04da65000000000, 0x7cf18c3200000000); + + return 0; +} |