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| author | Victor CLEMENT | 2015-06-02 15:56:23 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-06-02 15:56:25 +0200 |
| commit | 0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815 (patch) | |
| tree | 916e23e70af189de62e8ec74e4559a32234a8202 /thread-pool.c | |
| parent | target-arm: Add the GICv2m to the virt board (diff) | |
| download | qemu-0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815.tar.gz qemu-0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815.tar.xz qemu-0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815.zip | |
pl061: fix wrong calculation of GPIOMIS register
The masked interrupt status register should be the state of the interrupt
after masking.
There should be a logical AND instead of a logical OR between the
interrupt status and the interrupt mask.
Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1433154824-6927-1-git-send-email-victor.clement@openwide.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'thread-pool.c')
0 files changed, 0 insertions, 0 deletions