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| author | Blue Swirl | 2011-09-11 17:05:41 +0200 |
|---|---|---|
| committer | Blue Swirl | 2011-10-26 19:18:58 +0200 |
| commit | 11e66bca8ab0985e988e7c2fd019b743d79b4732 (patch) | |
| tree | a7ab48fcba8f7f02ad81708c3452ef6fa7dcbe9e /trace-events | |
| parent | Sparc: convert mmu_helper to trace framework (diff) | |
| download | qemu-11e66bca8ab0985e988e7c2fd019b743d79b4732.tar.gz qemu-11e66bca8ab0985e988e7c2fd019b743d79b4732.tar.xz qemu-11e66bca8ab0985e988e7c2fd019b743d79b4732.zip | |
Sparc: convert interrupt helpers to trace framework
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'trace-events')
| -rw-r--r-- | trace-events | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/trace-events b/trace-events index 7b5aa91a54..0cc1f66b93 100644 --- a/trace-events +++ b/trace-events @@ -609,3 +609,10 @@ mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64"" mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64"" mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64"" + +# target-sparc/int_helper.c +int_helper_set_softint(uint32_t softint) "new %08x" +int_helper_clear_softint(uint32_t softint) "new %08x" +int_helper_write_softint(uint32_t softint) "new %08x" +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" |