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author | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
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committer | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
commit | 2ecf17264debe1bc3399fe587690c78d03e8401b (patch) | |
tree | 792d6d3331647aff8e0d1e5a587b240bcb0d19dc /trace/ftrace.h | |
parent | hw/arm: ast2600: Correct the iBT interrupt ID (diff) | |
download | qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.gz qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.xz qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.zip |
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'trace/ftrace.h')
0 files changed, 0 insertions, 0 deletions