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author | Richard Henderson | 2019-09-30 05:59:46 +0200 |
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committer | Richard Henderson | 2019-10-14 16:10:33 +0200 |
commit | 7097312d37d3021cac9bb30a7f8c4660d2a25cd0 (patch) | |
tree | 5d31bf9b5a355b73ef0c422c4746ed7c177c6f52 /vl.c | |
parent | tcg/ppc: Update vector support for v2.07 VSX (diff) | |
download | qemu-7097312d37d3021cac9bb30a7f8c4660d2a25cd0.tar.gz qemu-7097312d37d3021cac9bb30a7f8c4660d2a25cd0.tar.xz qemu-7097312d37d3021cac9bb30a7f8c4660d2a25cd0.zip |
tcg/ppc: Update vector support for v2.07 FP
These new instructions are conditional on MSR.FP when TX=0 and
MSR.VEC when TX=1. Since we only care about the Altivec registers,
and force TX=1, we can consider these to be Altivec instructions.
Since Altivec is true for any use of vector types, we only need
test have_isa_2_07.
This includes moves to and from the integer registers.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'vl.c')
0 files changed, 0 insertions, 0 deletions