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-rw-r--r--hw/dma/puv3_dma.c9
-rw-r--r--hw/gpio/puv3_gpio.c15
-rw-r--r--hw/intc/puv3_intc.c9
-rw-r--r--hw/misc/puv3_pm.c9
-rw-r--r--hw/timer/puv3_ost.c9
-rw-r--r--hw/unicore32/puv3.c2
6 files changed, 39 insertions, 14 deletions
diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c
index 5488d388a9..7fa979180f 100644
--- a/hw/dma/puv3_dma.c
+++ b/hw/dma/puv3_dma.c
@@ -15,6 +15,7 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define PUV3_DMA_CH_NR (6)
#define PUV3_DMA_CH_MASK (0xff)
@@ -43,7 +44,9 @@ static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
ret = s->reg_CFG[PUV3_DMA_CH(offset)];
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
@@ -62,7 +65,9 @@ static void puv3_dma_write(void *opaque, hwaddr offset,
s->reg_CFG[PUV3_DMA_CH(offset)] = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}
diff --git a/hw/gpio/puv3_gpio.c b/hw/gpio/puv3_gpio.c
index d19e342514..7362b6715f 100644
--- a/hw/gpio/puv3_gpio.c
+++ b/hw/gpio/puv3_gpio.c
@@ -15,6 +15,7 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_GPIO "puv3_gpio"
#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
@@ -47,7 +48,9 @@ static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
ret = s->reg_GPIR;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
@@ -68,14 +71,16 @@ static void puv3_gpio_write(void *opaque, hwaddr offset,
if (s->reg_GPDR & value) {
s->reg_GPLR |= value;
} else {
- DPRINTF("Write gpio input port error!");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
+ __func__);
}
break;
case 0x0c:
if (s->reg_GPDR & value) {
s->reg_GPLR &= ~value;
} else {
- DPRINTF("Write gpio input port error!");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
+ __func__);
}
break;
case 0x10: /* GRER */
@@ -86,7 +91,9 @@ static void puv3_gpio_write(void *opaque, hwaddr offset,
s->reg_GPIR = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
}
diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c
index e018955ce8..090d4839d1 100644
--- a/hw/intc/puv3_intc.c
+++ b/hw/intc/puv3_intc.c
@@ -16,6 +16,7 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_INTC "puv3_intc"
#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
@@ -68,7 +69,9 @@ static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
ret = s->reg_ICPR; /* the same value with ICPR */
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
@@ -88,7 +91,9 @@ static void puv3_intc_write(void *opaque, hwaddr offset,
s->reg_ICMR = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
return;
}
puv3_intc_update(s);
diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c
index c213500d9c..8989d363cd 100644
--- a/hw/misc/puv3_pm.c
+++ b/hw/misc/puv3_pm.c
@@ -15,6 +15,7 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_PM "puv3_pm"
#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
@@ -73,7 +74,9 @@ static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
ret = 0x7;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
@@ -105,7 +108,9 @@ static void puv3_pm_write(void *opaque, hwaddr offset,
case 0x38:
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}
diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c
index 697519593b..f76b0bb1ca 100644
--- a/hw/timer/puv3_ost.c
+++ b/hw/timer/puv3_ost.c
@@ -14,6 +14,7 @@
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
@@ -52,7 +53,9 @@ static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
ret = s->reg_OIER;
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
@@ -88,7 +91,9 @@ static void puv3_ost_write(void *opaque, hwaddr offset,
s->reg_OIER = value;
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
}
diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
index 7f9c0238fe..eacacb4249 100644
--- a/hw/unicore32/puv3.c
+++ b/hw/unicore32/puv3.c
@@ -16,8 +16,6 @@
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/qtest.h"
-
-#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "hw/input/i8042.h"
#include "hw/irq.h"
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 11:56:14 +0100