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-rw-r--r--target/xtensa/fpu_helper.c22
-rw-r--r--target/xtensa/helper.h20
-rw-r--r--target/xtensa/translate.c70
3 files changed, 57 insertions, 55 deletions
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
index 87487293f9..46e231bdaa 100644
--- a/target/xtensa/fpu_helper.c
+++ b/target/xtensa/fpu_helper.c
@@ -33,7 +33,7 @@
#include "exec/exec-all.h"
#include "fpu/softfloat.h"
-void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
+void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
{
static const int rounding_mode[] = {
float_round_nearest_even,
@@ -56,33 +56,35 @@ float32 HELPER(neg_s)(float32 v)
return float32_chs(v);
}
-float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
+float32 HELPER(fpu2k_add_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_add(a, b, &env->fp_status);
}
-float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
+float32 HELPER(fpu2k_sub_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_sub(a, b, &env->fp_status);
}
-float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
+float32 HELPER(fpu2k_mul_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_mul(a, b, &env->fp_status);
}
-float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
+float32 HELPER(fpu2k_madd_s)(CPUXtensaState *env,
+ float32 a, float32 b, float32 c)
{
return float32_muladd(b, c, a, 0, &env->fp_status);
}
-float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
+float32 HELPER(fpu2k_msub_s)(CPUXtensaState *env,
+ float32 a, float32 b, float32 c)
{
return float32_muladd(b, c, a, float_muladd_negate_product,
&env->fp_status);
}
-uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
+uint32_t HELPER(ftoi_s)(float32 v, uint32_t rounding_mode, uint32_t scale)
{
float_status fp_status = {0};
@@ -90,7 +92,7 @@ uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
return float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status);
}
-uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
+uint32_t HELPER(ftoui_s)(float32 v, uint32_t rounding_mode, uint32_t scale)
{
float_status fp_status = {0};
float32 res;
@@ -106,13 +108,13 @@ uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
}
}
-float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
+float32 HELPER(itof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale)
{
return float32_scalbn(int32_to_float32(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
}
-float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
+float32 HELPER(uitof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale)
{
return float32_scalbn(uint32_to_float32(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h
index 8532de0b35..bce31cbd9f 100644
--- a/target/xtensa/helper.h
+++ b/target/xtensa/helper.h
@@ -46,18 +46,18 @@ DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32)
DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32)
#endif
-DEF_HELPER_2(wur_fcr, void, env, i32)
+DEF_HELPER_2(wur_fpu2k_fcr, void, env, i32)
DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_1(neg_s, TCG_CALL_NO_RWG_SE, f32, f32)
-DEF_HELPER_3(add_s, f32, env, f32, f32)
-DEF_HELPER_3(sub_s, f32, env, f32, f32)
-DEF_HELPER_3(mul_s, f32, env, f32, f32)
-DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
-DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
-DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32)
-DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32)
-DEF_HELPER_3(itof, f32, env, i32, i32)
-DEF_HELPER_3(uitof, f32, env, i32, i32)
+DEF_HELPER_3(fpu2k_add_s, f32, env, f32, f32)
+DEF_HELPER_3(fpu2k_sub_s, f32, env, f32, f32)
+DEF_HELPER_3(fpu2k_mul_s, f32, env, f32, f32)
+DEF_HELPER_4(fpu2k_madd_s, f32, env, f32, f32, f32)
+DEF_HELPER_4(fpu2k_msub_s, f32, env, f32, f32, f32)
+DEF_HELPER_FLAGS_3(ftoi_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32)
+DEF_HELPER_FLAGS_3(ftoui_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32)
+DEF_HELPER_3(itof_s, f32, env, i32, i32)
+DEF_HELPER_3(uitof_s, f32, env, i32, i32)
DEF_HELPER_4(un_s, void, env, i32, f32, f32)
DEF_HELPER_4(oeq_s, void, env, i32, f32, f32)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index bc01a72071..47951acd16 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2813,10 +2813,10 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
}
-static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
+static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
{
- gen_helper_wur_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
}
static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[],
@@ -5583,7 +5583,7 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){EXPSTATE},
}, {
.name = "wur.fcr",
- .translate = translate_wur_fcr,
+ .translate = translate_wur_fpu2k_fcr,
.par = (const uint32_t[]){FCR},
.coprocessor = 0x1,
}, {
@@ -6331,11 +6331,11 @@ static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[],
gen_helper_abs_s(arg[0].out, arg[1].in);
}
-static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
+static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
{
- gen_helper_add_s(arg[0].out, cpu_env,
- arg[1].in, arg[2].in);
+ gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ arg[1].in, arg[2].in);
}
enum {
@@ -6373,9 +6373,9 @@ static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
if (par[0]) {
- gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_s(arg[0].out, cpu_env, arg[1].in, scale);
} else {
- gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_s(arg[0].out, cpu_env, arg[1].in, scale);
}
tcg_temp_free(scale);
}
@@ -6387,11 +6387,11 @@ static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 scale = tcg_const_i32(arg[2].imm);
if (par[1]) {
- gen_helper_ftoui(arg[0].out, arg[1].in,
- rounding_mode, scale);
+ gen_helper_ftoui_s(arg[0].out, arg[1].in,
+ rounding_mode, scale);
} else {
- gen_helper_ftoi(arg[0].out, arg[1].in,
- rounding_mode, scale);
+ gen_helper_ftoi_s(arg[0].out, arg[1].in,
+ rounding_mode, scale);
}
tcg_temp_free(rounding_mode);
tcg_temp_free(scale);
@@ -6433,11 +6433,11 @@ static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],
tcg_temp_free(addr);
}
-static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
+static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
{
- gen_helper_madd_s(arg[0].out, cpu_env,
- arg[0].in, arg[1].in, arg[2].in);
+ gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ arg[0].in, arg[1].in, arg[2].in);
}
static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],
@@ -6471,18 +6471,18 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
tcg_temp_free(zero);
}
-static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
+static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
{
- gen_helper_mul_s(arg[0].out, cpu_env,
- arg[1].in, arg[2].in);
+ gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ arg[1].in, arg[2].in);
}
-static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
+static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
{
- gen_helper_msub_s(arg[0].out, cpu_env,
- arg[0].in, arg[1].in, arg[2].in);
+ gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ arg[0].in, arg[1].in, arg[2].in);
}
static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[],
@@ -6497,11 +6497,11 @@ static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(arg[0].out, arg[1].in);
}
-static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
- const uint32_t par[])
+static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
{
- gen_helper_sub_s(arg[0].out, cpu_env,
- arg[1].in, arg[2].in);
+ gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ arg[1].in, arg[2].in);
}
static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
@@ -6517,7 +6517,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.coprocessor = 0x1,
}, {
.name = "add.s",
- .translate = translate_add_s,
+ .translate = translate_fpu2k_add_s,
.coprocessor = 0x1,
}, {
.name = "ceil.s",
@@ -6560,7 +6560,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.coprocessor = 0x1,
}, {
.name = "madd.s",
- .translate = translate_madd_s,
+ .translate = translate_fpu2k_madd_s,
.coprocessor = 0x1,
}, {
.name = "mov.s",
@@ -6598,11 +6598,11 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.coprocessor = 0x1,
}, {
.name = "msub.s",
- .translate = translate_msub_s,
+ .translate = translate_fpu2k_msub_s,
.coprocessor = 0x1,
}, {
.name = "mul.s",
- .translate = translate_mul_s,
+ .translate = translate_fpu2k_mul_s,
.coprocessor = 0x1,
}, {
.name = "neg.s",
@@ -6658,7 +6658,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
.coprocessor = 0x1,
}, {
.name = "sub.s",
- .translate = translate_sub_s,
+ .translate = translate_fpu2k_sub_s,
.coprocessor = 0x1,
}, {
.name = "trunc.s",
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 21:44:51 +0100