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-rw-r--r--hw/xen/xen_pt_graphics.c2
-rw-r--r--scripts/coccinelle/exec_rw_const.cocci12
-rw-r--r--target/i386/hax-all.c4
3 files changed, 15 insertions, 3 deletions
diff --git a/hw/xen/xen_pt_graphics.c b/hw/xen/xen_pt_graphics.c
index b11e4e0546..a3bc7e3921 100644
--- a/hw/xen/xen_pt_graphics.c
+++ b/hw/xen/xen_pt_graphics.c
@@ -222,7 +222,7 @@ void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev,
}
/* Currently we fixed this address as a primary for legacy BIOS. */
- cpu_physical_memory_rw(0xc0000, bios, bios_size, true);
+ cpu_physical_memory_write(0xc0000, bios, bios_size);
}
uint32_t igd_read_opregion(XenPCIPassthroughState *s)
diff --git a/scripts/coccinelle/exec_rw_const.cocci b/scripts/coccinelle/exec_rw_const.cocci
index 35ab79e6d7..1a20296951 100644
--- a/scripts/coccinelle/exec_rw_const.cocci
+++ b/scripts/coccinelle/exec_rw_const.cocci
@@ -62,6 +62,18 @@ symbol true, false;
+ address_space_write(E1, E2, E3, E4, E5)
)
+// Avoid uses of cpu_physical_memory_rw() with a constant is_write argument.
+@@
+expression E1, E2, E3;
+@@
+(
+- cpu_physical_memory_rw(E1, E2, E3, false)
++ cpu_physical_memory_read(E1, E2, E3)
+|
+- cpu_physical_memory_rw(E1, E2, E3, true)
++ cpu_physical_memory_write(E1, E2, E3)
+)
+
// Remove useless cast
@@
expression E1, E2, E3, E4, E5, E6;
diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c
index 38936d7af6..f9c83fff25 100644
--- a/target/i386/hax-all.c
+++ b/target/i386/hax-all.c
@@ -376,8 +376,8 @@ static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft)
* hft->direction == 2: gpa ==> gpa2
*/
uint64_t value;
- cpu_physical_memory_rw(hft->gpa, &value, hft->size, false);
- cpu_physical_memory_rw(hft->gpa2, &value, hft->size, true);
+ cpu_physical_memory_read(hft->gpa, &value, hft->size);
+ cpu_physical_memory_write(hft->gpa2, &value, hft->size);
}
return 0;