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-rw-r--r--hw/alpha_typhoon.c10
-rw-r--r--hw/apic.c21
-rw-r--r--hw/arm/omap1.c4
-rw-r--r--hw/arm/pic_cpu.c5
-rw-r--r--hw/arm/pxa2xx.c7
-rw-r--r--hw/arm/pxa2xx_gpio.c2
-rw-r--r--hw/arm/pxa2xx_pic.c6
-rw-r--r--hw/cris/pic_cpu.c3
-rw-r--r--hw/i386/pc.c6
-rw-r--r--hw/i386/pc_piix.c3
-rw-r--r--hw/lm32/lm32_boards.c3
-rw-r--r--hw/lm32/milkymist.c3
-rw-r--r--hw/lpc_ich9.c2
-rw-r--r--hw/microblaze/pic_cpu.c3
-rw-r--r--hw/mips/mips_int.c2
-rw-r--r--hw/openrisc/pic_cpu.c2
-rw-r--r--hw/ppc/ppc.c6
-rw-r--r--hw/ppc/ppc405_uc.c4
-rw-r--r--hw/sh_intc.c5
-rw-r--r--hw/sparc/leon3.c3
-rw-r--r--hw/sparc/sun4m.c9
-rw-r--r--hw/sparc64/sun4u.c4
-rw-r--r--hw/unicore32/puv3.c3
-rw-r--r--hw/xtensa/pic_cpu.c2
24 files changed, 59 insertions, 59 deletions
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 7bfde5771c..770dc8cf0d 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -62,10 +62,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
{
/* If there are any non-masked interrupts, tell the cpu. */
if (cpu != NULL) {
- CPUAlphaState *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (req) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -359,11 +358,10 @@ static void cchip_write(void *opaque, hwaddr addr,
for (i = 0; i < 4; ++i) {
AlphaCPU *cpu = s->cchip.cpu[i];
if (cpu != NULL) {
- CPUAlphaState *env = &cpu->env;
CPUState *cs = CPU(cpu);
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
- cpu_interrupt(env, CPU_INTERRUPT_SMP);
+ cpu_interrupt(cs, CPU_INTERRUPT_SMP);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);
}
@@ -687,7 +685,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (i + 4);
/* And signal the interrupt. */
- cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER);
}
}
}
@@ -700,7 +698,7 @@ static void typhoon_alarm_timer(void *opaque)
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (cpu + 4);
- cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);
+ cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER);
}
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
diff --git a/hw/apic.c b/hw/apic.c
index cc9236a41c..d2395f04dd 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -151,15 +151,15 @@ static void apic_local_deliver(APICCommonState *s, int vector)
switch ((lvt >> 8) & 7) {
case APIC_DM_SMI:
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
break;
case APIC_DM_NMI:
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
break;
case APIC_DM_EXTINT:
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
break;
case APIC_DM_FIXED:
@@ -248,20 +248,20 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
case APIC_DM_SMI:
foreach_apic(apic_iter, deliver_bitmask,
- cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI)
+ cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
);
return;
case APIC_DM_NMI:
foreach_apic(apic_iter, deliver_bitmask,
- cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI)
+ cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
);
return;
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
foreach_apic(apic_iter, deliver_bitmask,
- cpu_interrupt(&apic_iter->cpu->env,
+ cpu_interrupt(CPU(apic_iter->cpu),
CPU_INTERRUPT_INIT)
);
return;
@@ -363,15 +363,16 @@ static int apic_irq_pending(APICCommonState *s)
/* signal the CPU if an irq is pending */
static void apic_update_irq(APICCommonState *s)
{
- CPUState *cpu = CPU(s->cpu);
+ CPUState *cpu;
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
return;
}
+ cpu = CPU(s->cpu);
if (!qemu_cpu_is_self(cpu)) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL);
+ cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
} else if (apic_irq_pending(s) > 0) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
}
}
@@ -478,7 +479,7 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
static void apic_startup(APICCommonState *s, int vector_num)
{
s->sipi_vector = vector_num;
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
}
void apic_sipi(DeviceState *d)
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index 7afd590ec7..3245c62e68 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -1523,7 +1523,7 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
omap_clk clk;
if (value & (1 << 11)) { /* SETARM_IDLE */
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
}
if (!(value & (1 << 10))) /* WKUP_MODE */
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
@@ -3759,7 +3759,7 @@ void omap_mpu_wakeup(void *opaque, int irq, int req)
CPUState *cpu = CPU(mpu->cpu);
if (cpu->halted) {
- cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB);
+ cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
diff --git a/hw/arm/pic_cpu.c b/hw/arm/pic_cpu.c
index 95f5bf1777..3a3f06566b 100644
--- a/hw/arm/pic_cpu.c
+++ b/hw/arm/pic_cpu.c
@@ -15,20 +15,19 @@
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
ARMCPU *cpu = opaque;
- CPUARMState *env = &cpu->env;
CPUState *cs = CPU(cpu);
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
case ARM_PIC_CPU_FIQ:
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_FIQ);
+ cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
}
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index c0f50c90fe..7467cca4f7 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -263,14 +263,14 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
/* Fall through. */
case 2:
/* Deep-Idle */
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
@@ -301,7 +301,8 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
#endif
/* Suspend */
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)),
+ CPU_INTERRUPT_HALT);
goto message;
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
index d2da928ac0..55ebcd724a 100644
--- a/hw/arm/pxa2xx_gpio.c
+++ b/hw/arm/pxa2xx_gpio.c
@@ -120,7 +120,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level)
/* Wake-up GPIOs */
if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
+ cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index b45b371435..25e90895e1 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -52,7 +52,7 @@ static void pxa2xx_pic_update(void *opaque)
mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
if (mask[0] || mask[1]) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
+ cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
@@ -60,13 +60,13 @@ static void pxa2xx_pic_update(void *opaque)
mask[1] = s->int_pending[1] & s->int_enabled[1];
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
+ cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
}
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
}
diff --git a/hw/cris/pic_cpu.c b/hw/cris/pic_cpu.c
index afd0df8041..85c68c0497 100644
--- a/hw/cris/pic_cpu.c
+++ b/hw/cris/pic_cpu.c
@@ -31,12 +31,11 @@
static void cris_pic_cpu_handler(void *opaque, int irq, int level)
{
CRISCPU *cpu = opaque;
- CPUCRISState *env = &cpu->env;
CPUState *cs = CPU(cpu);
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level) {
- cpu_interrupt(env, type);
+ cpu_interrupt(cs, type);
} else {
cpu_reset_interrupt(cs, type);
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c731bdc024..ed7d9badb5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -192,7 +192,7 @@ static void pic_irq_request(void *opaque, int irq, int level)
} else {
CPUState *cs = CPU(x86_env_get_cpu(env));
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -856,10 +856,10 @@ DeviceState *cpu_get_current_apic(void)
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
{
- CPUX86State *s = opaque;
+ X86CPU *cpu = opaque;
if (level) {
- cpu_interrupt(s, CPU_INTERRUPT_SMI);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
}
}
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0ee3b3b806..0abc9f11e3 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -205,7 +205,8 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled && acpi_enabled) {
i2c_bus *smbus;
- smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
+ smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt,
+ x86_env_get_cpu(first_cpu), 1);
/* TODO: Populate SPD eeprom data. */
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
gsi[9], *smi_irq,
diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c
index 538c20397f..db92948092 100644
--- a/hw/lm32/lm32_boards.c
+++ b/hw/lm32/lm32_boards.c
@@ -42,11 +42,10 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
LM32CPU *cpu = opaque;
- CPULM32State *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
index 9ff6d28854..b347cf964c 100644
--- a/hw/lm32/milkymist.c
+++ b/hw/lm32/milkymist.c
@@ -47,11 +47,10 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
LM32CPU *cpu = opaque;
- CPULM32State *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c
index 0ca0a59ef7..ff0a3092d5 100644
--- a/hw/lpc_ich9.c
+++ b/hw/lpc_ich9.c
@@ -381,7 +381,7 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
/* SMI_EN = PMBASE + 30. SMI control and enable register */
if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
- cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+ cpu_interrupt(CPU(x86_env_get_cpu(first_cpu)), CPU_INTERRUPT_SMI);
}
}
diff --git a/hw/microblaze/pic_cpu.c b/hw/microblaze/pic_cpu.c
index 47568505c7..6248de92bb 100644
--- a/hw/microblaze/pic_cpu.c
+++ b/hw/microblaze/pic_cpu.c
@@ -30,12 +30,11 @@
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
{
MicroBlazeCPU *cpu = opaque;
- CPUMBState *env = &cpu->env;
CPUState *cs = CPU(cpu);
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level) {
- cpu_interrupt(env, type);
+ cpu_interrupt(cs, type);
} else {
cpu_reset_interrupt(cs, type);
}
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 3a78999e02..0e5e86699c 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -40,7 +40,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index 7e4f9e015e..ca0b7c11bd 100644
--- a/hw/openrisc/pic_cpu.c
+++ b/hw/openrisc/pic_cpu.c
@@ -41,7 +41,7 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
for (i = 0; i < 32; i++) {
if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
- cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
cpu->env.picsr &= ~(1 << i);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index ae2ed70181..85bc821d94 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -58,7 +58,7 @@ void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
if (level) {
env->pending_interrupts |= 1 << n_IRQ;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
env->pending_interrupts &= ~(1 << n_IRQ);
if (env->pending_interrupts == 0) {
@@ -137,7 +137,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level)
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: reset the CPU\n", __func__);
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(cs, CPU_INTERRUPT_RESET);
}
break;
case PPC6xx_INPUT_SRESET:
@@ -219,7 +219,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level)
case PPC970_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(cs, CPU_INTERRUPT_RESET);
}
break;
case PPC970_INPUT_SRESET:
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8465f6dcd4..56bae8f6e0 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1776,7 +1776,7 @@ void ppc40x_core_reset(PowerPCCPU *cpu)
target_ulong dbsr;
printf("Reset PowerPC core\n");
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
@@ -1789,7 +1789,7 @@ void ppc40x_chip_reset(PowerPCCPU *cpu)
target_ulong dbsr;
printf("Reset PowerPC chip\n");
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index 97903140ab..29e3d8f127 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -45,8 +45,9 @@ void sh_intc_toggle_source(struct intc_source *source,
CPUState *cpu = CPU(sh_env_get_cpu(first_cpu));
if (source->pending) {
source->parent->pending++;
- if (source->parent->pending == 1)
- cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+ if (source->parent->pending == 1) {
+ cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
+ }
} else {
source->parent->pending--;
if (source->parent->pending == 0) {
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index b1fbde0ff7..bf06bf4b51 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -83,8 +83,9 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
+ cs = CPU(sparc_env_get_cpu(env));
trace_leon3_set_irq(i);
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index a1822f16f3..2f214da557 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -242,8 +242,9 @@ void cpu_check_irqs(CPUSPARCState *env)
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
+ cs = CPU(sparc_env_get_cpu(env));
trace_sun4m_cpu_interrupt(i);
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
@@ -306,8 +307,10 @@ static void secondary_cpu_reset(void *opaque)
static void cpu_halt_signal(void *opaque, int irq, int level)
{
- if (level && cpu_single_env)
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
+ if (level && cpu_single_env) {
+ cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)),
+ CPU_INTERRUPT_HALT);
+ }
}
static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 817c23cde3..4c39cf6607 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -299,7 +299,7 @@ void cpu_check_irqs(CPUSPARCState *env)
env->interrupt_index = new_interrupt;
CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
old_interrupt, new_interrupt);
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
@@ -339,7 +339,7 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level)
env->ivec_data[0] = (0x1f << 6) | irq;
env->ivec_data[1] = 0;
env->ivec_data[2] = 0;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
} else {
if (env->ivec_status & 0x20) {
diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
index 6e87c41f28..78ab13f9ed 100644
--- a/hw/unicore32/puv3.c
+++ b/hw/unicore32/puv3.c
@@ -27,12 +27,11 @@
static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
{
UniCore32CPU *cpu = opaque;
- CPUUniCore32State *env = &cpu->env;
CPUState *cs = CPU(cpu);
assert(irq == 0);
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c
index fd590c64ce..7f015ff5ab 100644
--- a/hw/xtensa/pic_cpu.c
+++ b/hw/xtensa/pic_cpu.c
@@ -66,7 +66,7 @@ void check_interrupts(CPUXtensaState *env)
for (level = env->config->nlevel; level > minlevel; --level) {
if (env->config->level_mask[level] & int_set_enabled) {
env->pending_irq_level = level;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
qemu_log_mask(CPU_LOG_INT,
"%s level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 08:55:51 +0100