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-rw-r--r--include/hw/arm/aspeed_soc.h4
-rw-r--r--include/hw/gpio/aspeed_gpio.h100
-rw-r--r--include/hw/misc/aspeed_scu.h21
-rw-r--r--include/hw/ssi/aspeed_smc.h7
4 files changed, 126 insertions, 6 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 976fd6be93..ab5052b12c 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -23,6 +23,7 @@
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
+#include "hw/gpio/aspeed_gpio.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_WDTS_NUM 3
@@ -48,6 +49,7 @@ typedef struct AspeedSoCState {
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
+ AspeedGPIOState gpio;
} AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -59,8 +61,6 @@ typedef struct AspeedSoCInfo {
uint32_t silicon_rev;
uint64_t sram_size;
int spis_num;
- const char *fmc_typename;
- const char **spi_typename;
int wdts_num;
const int *irqmap;
const hwaddr *memmap;
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
new file mode 100644
index 0000000000..a2deac046a
--- /dev/null
+++ b/include/hw/gpio/aspeed_gpio.h
@@ -0,0 +1,100 @@
+/*
+ * ASPEED GPIO Controller
+ *
+ * Copyright (C) 2017-2018 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef ASPEED_GPIO_H
+#define ASPEED_GPIO_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_GPIO "aspeed.gpio"
+#define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO)
+#define ASPEED_GPIO_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO)
+#define ASPEED_GPIO_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO)
+
+#define ASPEED_GPIO_MAX_NR_SETS 8
+#define ASPEED_REGS_PER_BANK 14
+#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
+#define ASPEED_GPIO_NR_PINS 228
+#define ASPEED_GROUPS_PER_SET 4
+#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
+#define ASPEED_CHARS_PER_GROUP_LABEL 4
+
+typedef struct GPIOSets GPIOSets;
+
+typedef struct GPIOSetProperties {
+ uint32_t input;
+ uint32_t output;
+ char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
+} GPIOSetProperties;
+
+enum GPIORegType {
+ gpio_not_a_reg,
+ gpio_reg_data_value,
+ gpio_reg_direction,
+ gpio_reg_int_enable,
+ gpio_reg_int_sens_0,
+ gpio_reg_int_sens_1,
+ gpio_reg_int_sens_2,
+ gpio_reg_int_status,
+ gpio_reg_reset_tolerant,
+ gpio_reg_debounce_1,
+ gpio_reg_debounce_2,
+ gpio_reg_cmd_source_0,
+ gpio_reg_cmd_source_1,
+ gpio_reg_data_read,
+ gpio_reg_input_mask,
+};
+
+typedef struct AspeedGPIOReg {
+ uint16_t set_idx;
+ enum GPIORegType type;
+ } AspeedGPIOReg;
+
+typedef struct AspeedGPIOClass {
+ SysBusDevice parent_obj;
+ const GPIOSetProperties *props;
+ uint32_t nr_gpio_pins;
+ uint32_t nr_gpio_sets;
+ uint32_t gap;
+ const AspeedGPIOReg *reg_table;
+} AspeedGPIOClass;
+
+typedef struct AspeedGPIOState {
+ /* <private> */
+ SysBusDevice parent;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ int pending;
+ qemu_irq irq;
+ qemu_irq gpios[ASPEED_GPIO_NR_PINS];
+
+/* Parallel GPIO Registers */
+ uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
+ struct GPIOSets {
+ uint32_t data_value; /* Reflects pin values */
+ uint32_t data_read; /* Contains last value written to data value */
+ uint32_t direction;
+ uint32_t int_enable;
+ uint32_t int_sens_0;
+ uint32_t int_sens_1;
+ uint32_t int_sens_2;
+ uint32_t int_status;
+ uint32_t reset_tol;
+ uint32_t cmd_source_0;
+ uint32_t cmd_source_1;
+ uint32_t debounce_1;
+ uint32_t debounce_2;
+ uint32_t input_mask;
+ } sets[ASPEED_GPIO_MAX_NR_SETS];
+} AspeedGPIOState;
+
+#endif /* _ASPEED_GPIO_H_ */
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 38996adc59..239e94fe2c 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -15,6 +15,8 @@
#define TYPE_ASPEED_SCU "aspeed.scu"
#define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU)
+#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
+#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
@@ -30,10 +32,6 @@ typedef struct AspeedSCUState {
uint32_t hw_strap1;
uint32_t hw_strap2;
uint32_t hw_prot_key;
-
- uint32_t clkin;
- uint32_t hpll;
- uint32_t apb_freq;
} AspeedSCUState;
#define AST2400_A0_SILICON_REV 0x02000303U
@@ -45,8 +43,23 @@ typedef struct AspeedSCUState {
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
+#define ASPEED_SCU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedSCUClass, (klass), TYPE_ASPEED_SCU)
+#define ASPEED_SCU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedSCUClass, (obj), TYPE_ASPEED_SCU)
+
+typedef struct AspeedSCUClass {
+ SysBusDeviceClass parent_class;
+
+ const uint32_t *resets;
+ uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
+ uint32_t apb_divider;
+} AspeedSCUClass;
+
#define ASPEED_SCU_PROT_KEY 0x1688A8A8
+uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
+
/*
* Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
* were added.
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index aa07dac4fe..5176ff6bf9 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -46,6 +46,8 @@ typedef struct AspeedSMCController {
hwaddr flash_window_base;
uint32_t flash_window_size;
bool has_dma;
+ hwaddr dma_flash_mask;
+ hwaddr dma_dram_mask;
uint32_t nregs;
} AspeedSMCController;
@@ -86,6 +88,7 @@ typedef struct AspeedSMCState {
uint32_t num_cs;
qemu_irq *cs_lines;
+ bool inject_failure;
SSIBus *spi;
@@ -101,6 +104,10 @@ typedef struct AspeedSMCState {
/* for DMA support */
uint64_t sdram_base;
+ AddressSpace flash_as;
+ MemoryRegion *dram_mr;
+ AddressSpace dram_as;
+
AspeedSMCFlash *flashes;
uint8_t snoop_index;
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-05-08 07:31:33 +0200