diff options
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4cbc31c3e8..b9e227a30e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -828,7 +828,7 @@ struct CPUMIPSState { #define CP0EBase_WG 11 target_ulong CP0_CMGCRBase; /* - * CP0 Register 16 + * CP0 Register 16 (after Release 1) */ int32_t CP0_Config0; #define CP0C0_M 31 @@ -845,6 +845,14 @@ struct CPUMIPSState { #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ #define CP0C0_AR_LENGTH 3 +/* + * CP0 Register 16 (before Release 1) + */ +#define CP0C0_Impl 16 /* 24..16 */ +#define CP0C0_IC 9 /* 11..9 */ +#define CP0C0_DC 6 /* 8..6 */ +#define CP0C0_IB 5 +#define CP0C0_DB 4 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ @@ -1291,12 +1299,23 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); +/* Check presence of MSA implementation */ +static inline bool ase_msa_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MSAP); +} + /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MT); } +static inline bool cpu_type_is_64bit(const char *cpu_type) +{ + return cpu_type_supports_isa(cpu_type, CPU_MIPS64); +} + void cpu_set_exception_base(int vp_index, target_ulong address); /* addr.c */ @@ -1304,6 +1323,8 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); +uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); +uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); bool mips_um_ksegs_enabled(void); void mips_um_ksegs_enable(void); |