summaryrefslogtreecommitdiffstats
path: root/target/mips/cpu.h
Commit message (Expand)AuthorAgeFilesLines
* target/mips: Use an exception for semihostingRichard Henderson2022-06-281-1/+2
* target/mips: Fix emulation of nanoMIPS BPOSGE32C instructionDragan Mladjenovic2022-06-111-1/+1
* target/mips: Fix WatchHi.M handlingMarcin Nowakowski2022-06-111-0/+1
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-1/+1
* Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into stagingPeter Maydell2022-03-091-9/+0Star
|\
| * target/mips: Remove duplicated MIPSCPU::cp0_count_ratePhilippe Mathieu-Daudé2022-03-071-9/+0Star
* | target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* | target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-2/+0Star
* | target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-4/+2Star
|/
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-3/+0Star
* target/mips: Restrict some system specific declarations to sysemuPhilippe Mathieu-Daudé2021-06-241-3/+7
* target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé2021-02-211-3/+7
* target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé2021-02-211-16/+0Star
* target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé2021-01-141-0/+6
* target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-141-0/+5
* target/mips/addr: Add translation helpers for KSEG1Jiaxun Yang2021-01-141-0/+2
* target/mips: Add CP0 Config0 register definitions for MIPS3 ISAPhilippe Mathieu-Daudé2021-01-141-1/+9
* linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macroPhilippe Mathieu-Daudé2020-12-171-0/+1
* target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-131-0/+7
* hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé2020-12-131-0/+8
* target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argumentPhilippe Mathieu-Daudé2020-12-131-0/+1
* target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé2020-12-131-2/+2
* target/mips: Fix PageMask with variable page sizeJiaxun Yang2020-11-091-0/+1
* target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé2020-10-171-0/+12
* target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé2020-10-171-0/+4
* target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé2020-10-171-0/+9
* target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé2020-10-171-0/+1
* target/mips: Add Loongson-3 CPU definitionHuacai Chen2020-06-091-2/+30
* target/mips: Add implementation of GINVT instructionYongbok Kim2020-01-291-1/+1
* target/mips: Amend CP0 WatchHi register implementationYongbok Kim2020-01-291-1/+1
* target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIXRichard Henderson2020-01-161-4/+0Star
* target/mips: Clean up handling of CP0 register 31Aleksandar Markovic2019-08-291-1/+1
* target/mips: Clean up handling of CP0 register 29Aleksandar Markovic2019-08-291-8/+14
* target/mips: Clean up handling of CP0 register 28Aleksandar Markovic2019-08-291-10/+14
* target/mips: Clean up handling of CP0 register 26Aleksandar Markovic2019-08-291-1/+1
* target/mips: Clean up handling of CP0 register 23Aleksandar Markovic2019-08-291-0/+6
* target/mips: Clean up handling of CP0 register 19Aleksandar Markovic2019-08-291-0/+4
* target/mips: Clean up handling of CP0 register 18Aleksandar Markovic2019-08-291-8/+12
* target/mips: Clean up handling of CP0 register 16Aleksandar Markovic2019-08-291-1/+2
* target/mips: Clean up handling of CP0 register 15Aleksandar Markovic2019-08-291-0/+1
* target/mips: Clean up handling of CP0 register 14Aleksandar Markovic2019-08-291-0/+1
* target/mips: Clean up handling of CP0 register 13Aleksandar Markovic2019-08-291-0/+2
* target/mips: Clean up handling of CP0 register 12Aleksandar Markovic2019-08-291-0/+3
* target/mips: Clean up handling of CP0 register 10Aleksandar Markovic2019-08-291-0/+1
* target/mips: Clean up handling of CP0 register 8Aleksandar Markovic2019-08-291-0/+1
* target/mips: Clean up handling of CP0 register 6Aleksandar Markovic2019-08-291-0/+6
* target/mips: Clean up handling of CP0 register 5Aleksandar Markovic2019-08-291-0/+6
* target/mips: Clean up handling of CP0 register 4Aleksandar Markovic2019-08-291-0/+2
* target/mips: Clean up handling of CP0 register 3Aleksandar Markovic2019-08-291-0/+1
* target/mips: Clean up handling of CP0 register 2Aleksandar Markovic2019-08-291-0/+7