diff options
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 262 |
1 files changed, 0 insertions, 262 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index c64a1bc42e..19933b7868 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24,12 +24,8 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "disas/disas.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" -#include "hw/mips/cpudevs.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" @@ -31757,264 +31753,6 @@ void mips_tcg_init(void) #endif } -#include "translate_init.c.inc" - -void cpu_mips_realize_env(CPUMIPSState *env) -{ - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, env->cpu_model); -#endif - fpu_init(env, env->cpu_model); - mvp_init(env, env->cpu_model); -} - -bool cpu_supports_cps_smp(const char *cpu_type) -{ - const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); - return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; -} - -bool cpu_supports_isa(const char *cpu_type, uint64_t isa) -{ - const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); - return (mcc->cpu_def->insn_flags & isa) != 0; -} - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base = address; -} - -void cpu_state_reset(CPUMIPSState *env) -{ - CPUState *cs = env_cpu(env); - - /* Reset registers to their default values */ - env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; -#ifdef TARGET_WORDS_BIGENDIAN - env->CP0_Config0 |= (1 << CP0C0_BE); -#endif - env->CP0_Config1 = env->cpu_model->CP0_Config1; - env->CP0_Config2 = env->cpu_model->CP0_Config2; - env->CP0_Config3 = env->cpu_model->CP0_Config3; - env->CP0_Config4 = env->cpu_model->CP0_Config4; - env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; - env->CP0_Config5 = env->cpu_model->CP0_Config5; - env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; - env->CP0_Config6 = env->cpu_model->CP0_Config6; - env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; - env->CP0_Config7 = env->cpu_model->CP0_Config7; - env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; - env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask - << env->cpu_model->CP0_LLAddr_shift; - env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; - env->SYNCI_Step = env->cpu_model->SYNCI_Step; - env->CCRes = env->cpu_model->CCRes; - env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; - env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; - env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; - env->current_tc = 0; - env->SEGBITS = env->cpu_model->SEGBITS; - env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); -#if defined(TARGET_MIPS64) - if (env->cpu_model->insn_flags & ISA_MIPS3) { - env->SEGMask |= 3ULL << 62; - } -#endif - env->PABITS = env->cpu_model->PABITS; - env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; - env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; - env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; - env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; - env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; - env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; - env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; - env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; - env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; - env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; - env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; - env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; - env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; - env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; - env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; - env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; - env->msair = env->cpu_model->MSAIR; - env->insn_flags = env->cpu_model->insn_flags; - -#if defined(CONFIG_USER_ONLY) - env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); -# ifdef TARGET_MIPS64 - /* Enable 64-bit register mode. */ - env->CP0_Status |= (1 << CP0St_PX); -# endif -# ifdef TARGET_ABI_MIPSN64 - /* Enable 64-bit address mode. */ - env->CP0_Status |= (1 << CP0St_UX); -# endif - /* - * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR - * hardware registers. - */ - env->CP0_HWREna |= 0x0000000F; - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - env->CP0_Status |= (1 << CP0St_CU1); - } - if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { - env->CP0_Status |= (1 << CP0St_MX); - } -# if defined(TARGET_MIPS64) - /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ - if ((env->CP0_Config1 & (1 << CP0C1_FP)) && - (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - env->CP0_Status |= (1 << CP0St_FR); - } -# endif -#else - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, - * come back to the jump. - */ - env->CP0_ErrorEPC = (env->active_tc.PC - - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); - } else { - env->CP0_ErrorEPC = env->active_tc.PC; - } - env->active_tc.PC = env->exception_base; - env->CP0_Random = env->tlb->nb_tlb - 1; - env->tlb->tlb_in_use = env->tlb->nb_tlb; - env->CP0_Wired = 0; - env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; - env->CP0_EBase = (cs->cpu_index & 0x3FF); - if (mips_um_ksegs_enabled()) { - env->CP0_EBase |= 0x40000000; - } else { - env->CP0_EBase |= (int32_t)0x80000000; - } - if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { - env->CP0_CMGCRBase = 0x1fbf8000 >> 4; - } - env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? - 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; - env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); - /* - * Vectored interrupts not implemented, timer on int 7, - * no performance counters. - */ - env->CP0_IntCtl = 0xe0000000; - { - int i; - - for (i = 0; i < 7; i++) { - env->CP0_WatchLo[i] = 0; - env->CP0_WatchHi[i] = 0x80000000; - } - env->CP0_WatchLo[7] = 0; - env->CP0_WatchHi[7] = 0; - } - /* Count register increments in debug mode, EJTAG version 1 */ - env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); - - cpu_mips_store_count(env, 1); - - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - int i; - - /* Only TC0 on VPE 0 starts as active. */ - for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { - env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; - env->tcs[i].CP0_TCHalt = 1; - } - env->active_tc.CP0_TCHalt = 1; - cs->halted = 1; - - if (cs->cpu_index == 0) { - /* VPE0 starts up enabled. */ - env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); - env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); - - /* TC0 starts up unhalted. */ - cs->halted = 0; - env->active_tc.CP0_TCHalt = 0; - env->tcs[0].CP0_TCHalt = 0; - /* With thread 0 active. */ - env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); - env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); - } - } - - /* - * Configure default legacy segmentation control. We use this regardless of - * whether segmentation control is presented to the guest. - */ - /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ - env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); - /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ - env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; - /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ - env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | - (2 << CP0SC_C); - /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ - env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | - (3 << CP0SC_C)) << 16; - /* USeg (seg4 0x40000000..0x7FFFFFFF) */ - env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | - (1 << CP0SC_EU) | (2 << CP0SC_C); - /* USeg (seg5 0x00000000..0x3FFFFFFF) */ - env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | - (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; - /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ - env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); -#endif - if ((env->insn_flags & ISA_MIPS32R6) && - (env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ - env->CP0_Status |= (1 << CP0St_FR); - } - - if (env->insn_flags & ISA_MIPS32R6) { - /* PTW = 1 */ - env->CP0_PWSize = 0x40; - /* GDI = 12 */ - /* UDI = 12 */ - /* MDI = 12 */ - /* PRI = 12 */ - /* PTEI = 2 */ - env->CP0_PWField = 0x0C30C302; - } else { - /* GDI = 0 */ - /* UDI = 0 */ - /* MDI = 0 */ - /* PRI = 0 */ - /* PTEI = 2 */ - env->CP0_PWField = 0x02; - } - - if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { - /* microMIPS on reset when Config3.ISA is 3 */ - env->hflags |= MIPS_HFLAG_M16; - } - - /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { - msa_reset(env); - } - - compute_hflags(env); - restore_fp_status(env); - restore_pamask(env); - cs->exception_index = EXCP_NONE; - - if (semihosting_get_argc()) { - /* UHI interface can be used to obtain argc and argv */ - env->active_tc.gpr[4] = -1; - } -} - void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, target_ulong *data) { |