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-rw-r--r--target/mips/translate.c28
-rw-r--r--target/mips/translate.h1
2 files changed, 17 insertions, 12 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2139109744..a1a9a85008 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] = {
"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
};
-#endif
+
+void mxu_translate_init(void)
+{
+ for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
+ mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
+ mxuregnames[i]);
+ }
+
+ mxu_CR = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState, active_tc.mxu_cr),
+ mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
+}
+#endif /* !TARGET_MIPS64 */
/* General purpose registers moves. */
void gen_load_gpr(TCGv t, int reg)
@@ -28047,18 +28060,9 @@ void mips_tcg_init(void)
cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
"llval");
-#if !defined(TARGET_MIPS64)
- for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
- mxu_gpr[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUMIPSState,
- active_tc.mxu_gpr[i]),
- mxuregnames[i]);
+ if (TARGET_LONG_BITS == 32) {
+ mxu_translate_init();
}
-
- mxu_CR = tcg_global_mem_new(cpu_env,
- offsetof(CPUMIPSState, active_tc.mxu_cr),
- mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
-#endif /* !TARGET_MIPS64 */
}
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
diff --git a/target/mips/translate.h b/target/mips/translate.h
index a5c49f1ee2..a807b3d256 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -179,6 +179,7 @@ extern TCGv bcond;
void msa_translate_init(void);
/* MXU */
+void mxu_translate_init(void);
bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
/* decodetree generated */