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-rw-r--r--target/riscv/insn_trans/trans_rvc.inc.c144
1 files changed, 11 insertions, 133 deletions
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 3e5d6fd5ea..e840ac40df 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
return trans_addi(ctx, &arg);
}
-static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
{
#ifdef TARGET_RISCV32
@@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- arg_c_lw tmp;
- decode_insn16_extract_cl_w(ctx, &tmp, ctx->opcode);
- arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+ arg_i arg;
+ decode_insn16_extract_cl_w(ctx, &arg, ctx->opcode);
return trans_flw(ctx, &arg);
#else
/* C.LD ( RV64C/RV128C-only ) */
- arg_c_fld tmp;
- decode_insn16_extract_cl_d(ctx, &tmp, ctx->opcode);
- arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+ arg_i arg;
+ decode_insn16_extract_cl_d(ctx, &arg, ctx->opcode);
return trans_ld(ctx, &arg);
#endif
}
-static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
-{
- arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
-{
- arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
-
static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
{
#ifdef TARGET_RISCV32
@@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- arg_c_sw tmp;
- decode_insn16_extract_cs_w(ctx, &tmp, ctx->opcode);
- arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+ arg_s arg;
+ decode_insn16_extract_cs_w(ctx, &arg, ctx->opcode);
return trans_fsw(ctx, &arg);
#else
/* C.SD ( RV64C/RV128C-only ) */
- arg_c_fsd tmp;
- decode_insn16_extract_cs_d(ctx, &tmp, ctx->opcode);
- arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+ arg_s arg;
+ decode_insn16_extract_cs_d(ctx, &arg, ctx->opcode);
return trans_sd(ctx, &arg);
#endif
}
-static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
-{
- if (a->imm == 0) {
- /* Hint: insn is valid but does not affect state */
- return true;
- }
- arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_addi(ctx, &arg);
-}
-
static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
{
#ifdef TARGET_RISCV32
/* C.JAL */
- arg_c_j tmp;
+ arg_j tmp;
decode_insn16_extract_cj(ctx, &tmp, ctx->opcode);
arg_jal arg = { .rd = 1, .imm = tmp.imm };
return trans_jal(ctx, &arg);
@@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
#endif
}
-static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
-{
- if (a->rd == 0) {
- /* Hint: insn is valid but does not affect state */
- return true;
- }
- arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
- return trans_addi(ctx, &arg);
-}
-
static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
{
if (a->rd == 2) {
@@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
return trans_srai(ctx, &arg);
}
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
- arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
-{
- arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_sub(ctx, &arg);
-}
-
-static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
-{
- arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_xor(ctx, &arg);
-}
-
-static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
-{
- arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_or(ctx, &arg);
-}
-
-static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
-{
- arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_and(ctx, &arg);
-}
-
static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
{
#ifdef TARGET_RISCV64
- arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_subw(ctx, &arg);
+ return trans_subw(ctx, a);
#else
return false;
#endif
@@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
{
#ifdef TARGET_RISCV64
- arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_addw(ctx, &arg);
+ return trans_addw(ctx, a);
#else
return false;
#endif
}
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
- arg_jal arg = { .rd = 0, .imm = a->imm };
- return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
- arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
- arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_bne(ctx, &arg);
-}
-
static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
{
int shamt = a->shamt;
@@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
return trans_slli(ctx, &arg);
}
-static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
{
#ifdef TARGET_RISCV32
@@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
return false;
}
-static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
-{
- arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
-{
- arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
-
static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
{
#ifdef TARGET_RISCV32
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 09:53:44 +0100