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* target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu2022-09-271-2/+4
* target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell2022-09-131-1/+2
* target/riscv: Add Zihintpause supportDao Lu2022-09-071-0/+16
* target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen2022-09-071-0/+1
* target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen2022-09-071-0/+3
* target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen2022-09-071-0/+12
* target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen2022-09-071-0/+1
* target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen2022-09-071-0/+1
* target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen2022-09-071-0/+2
* target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen2022-09-071-0/+5
* target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen2022-09-071-0/+3
* target/riscv: Minimize the calls to decode_save_opcRichard Henderson2022-07-033-0/+8
* target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo2022-07-031-6/+2Star
* target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis2022-06-101-2/+10
* target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD2022-06-101-2/+5
* target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD2022-06-101-0/+6
* target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD2022-06-101-0/+17
* target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD2022-06-101-4/+8
* target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD2022-06-101-1/+2
* target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD2022-06-101-2/+11
* target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD2022-06-101-0/+6
* target/riscv: rvv: Add tail agnostic for vv instructionseopXD2022-06-101-1/+2
* target/riscv: rvv: Early exit when vstart >= vleopXD2022-06-101-0/+27
* target/riscv: add support for zmmul extension v0.1Weiwei Li2022-06-101-6/+12
* target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD2022-05-241-27/+31
* target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li2022-04-291-0/+58
* target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li2022-04-291-0/+53
* target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li2022-04-291-0/+100
* target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li2022-04-291-0/+55
* target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li2022-04-291-0/+54
* target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li2022-04-291-0/+71
* target/riscv: rvk: add support for zbkx extensionWeiwei Li2022-04-291-0/+18
* target/riscv: rvk: add support for zbkc extensionWeiwei Li2022-04-291-2/+2
* target/riscv: rvk: add support for zbkb extensionWeiwei Li2022-04-291-12/+82
* target/riscv: optimize helper for vmv<nr>r.vWeiwei Li2022-04-221-11/+6Star
* target/riscv: optimize condition assign for scale < 0Weiwei Li2022-04-221-5/+3Star
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-2/+2
* target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen2022-04-011-0/+5
* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-031-95/+237
* target/riscv: add support for zdinxWeiwei Li2022-03-031-78/+207
* target/riscv: add support for zfinxWeiwei Li2022-03-031-96/+218
* target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich2022-03-031-4/+4
* target/riscv: add support for svinval extensionWeiwei Li2022-02-161-0/+75
* target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich2022-02-161-0/+39
* target/riscv: access cfg structure through DisasContextPhilipp Tomsich2022-02-161-4/+4
* target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich2022-02-163-55/+97
* target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei2022-01-211-1/+1
* target/riscv: Calculate address according to XLENLIU Zhiwei2022-01-214-56/+9Star
* target/riscv: Adjust csr write mask with XLENLIU Zhiwei2022-01-211-4/+8
* target/riscv: Sign extend pc for different XLENLIU Zhiwei2022-01-213-5/+6
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