diff options
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 4 | ||||
| -rw-r--r-- | target/riscv/vector_helper.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 4ea7e41e1a..8d675db9a2 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3293,7 +3293,7 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base, /* offset of the idx element with base regsiter r */ static uint32_t endian_ofs(DisasContext *s, int r, int idx) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew); #else return vreg_ofs(s, r) + (idx << s->sew); @@ -3303,7 +3303,7 @@ static uint32_t endian_ofs(DisasContext *s, int r, int idx) /* adjust the index according to the endian */ static void endian_adjust(TCGv_i32 ofs, int sew) { -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN tcg_gen_xori_i32(ofs, ofs, 7 >> sew); #endif } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3bd4aac9c9..7a6ce0a3bc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -79,7 +79,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, * Note that vector data is stored in host-endian 64-bit chunks, * so addressing units smaller than that needs a host-endian fixup. */ -#ifdef HOST_WORDS_BIGENDIAN +#if HOST_BIG_ENDIAN #define H1(x) ((x) ^ 7) #define H1_2(x) ((x) ^ 6) #define H1_4(x) ((x) ^ 4) |