summaryrefslogtreecommitdiffstats
path: root/target/riscv
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2022-10-261-2/+7
|\
| * target/riscv: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-2/+7
* | treewide: Remove the unnecessary space before semicolonBin Meng2022-10-241-1/+1
|/
* target/riscv: pmp: Fixup TLB size calculationAlistair Francis2022-10-141-0/+12
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2022-10-131-0/+4
|\
| * kvm: allow target-specific accelerator propertiesPaolo Bonzini2022-10-101-0/+4
* | dump: Replace opaque DumpState pointer with a typed oneJanosch Frank2022-10-062-6/+4Star
|/
* accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-041-2/+2
* hw/core: Add CPUClass.get_pcRichard Henderson2022-10-041-0/+13
* target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu2022-09-274-15/+31
* target/riscv: rvv-1.0: Simplify vfwredsum codeYang Liu2022-09-271-46/+10Star
* target/riscv: debug: Add initial support of type 6 triggerFrank Chang2022-09-272-4/+188
* target/riscv: debug: Check VU/VS modes for type 2 triggerFrank Chang2022-09-271-0/+10
* target/riscv: debug: Create common trigger actions functionFrank Chang2022-09-272-2/+70
* target/riscv: debug: Introduce tinfo CSRFrank Chang2022-09-274-3/+18
* target/riscv: debug: Restrict the range of tselect value can be writtenFrank Chang2022-09-271-6/+3Star
* target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang2022-09-274-88/+48Star
* target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang2022-09-272-5/+12
* target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang2022-09-275-67/+140
* target/riscv: Check the correct exception cause in vector GDB stubFrank Chang2022-09-261-2/+2
* target/riscv: Set the CPU resetvec directlyAlistair Francis2022-09-263-15/+7Star
* target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xmlAndrew Burgess2022-09-261-30/+2Star
* target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li2022-09-261-4/+9
* target/riscv: Remove sideleg and sedelegRahul Pathak2022-09-261-2/+0Star
* target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell2022-09-133-7/+6Star
* target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra2022-09-071-30/+60
* hw/riscv: virt: Add PMU DT node to the device treeAtish Patra2022-09-072-0/+58
* target/riscv: Add few cache related PMU eventsAtish Patra2022-09-071-0/+25
* target/riscv: Simplify counter predicate functionAtish Patra2022-09-071-101/+9Star
* target/riscv: Add sscofpmf extension supportAtish Patra2022-09-077-11/+623
* target/riscv: Add vstimecmp supportAtish Patra2022-09-076-6/+118
* target/riscv: Add stimecmp supportAtish Patra2022-09-078-1/+235
* hw/intc: Move mtimer/mtimecmp to aclintAtish Patra2022-09-072-5/+2Star
* target/riscv: Use official extension names for AIA CSRsAnup Patel2022-09-074-14/+26
* target/riscv: Add xicondops in ISA entryRahul Pathak2022-09-071-0/+1
* target/riscv: Remove additional priv version check for mcountinhibitAtish Patra2022-09-071-8/+0Star
* target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li2022-09-071-19/+25
* target/riscv: Add Zihintpause supportDao Lu2022-09-074-1/+25
* target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD2022-09-071-0/+1
* target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen2022-09-072-2/+25
* target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen2022-09-072-0/+14
* target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen2022-09-072-0/+38
* target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...Yueh-Ting (eop) Chen2022-09-071-10/+16
* target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen2022-09-072-0/+11
* target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen2022-09-072-0/+8
* target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen2022-09-072-0/+5
* target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen2022-09-072-11/+29
* target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen2022-09-076-2/+20
* target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo2022-09-071-1/+1
* target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li2022-09-071-13/+5Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 15:50:21 +0100