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-rw-r--r--target/sparc/cpu-qom.h2
-rw-r--r--target/sparc/cpu.c391
-rw-r--r--target/sparc/cpu.h11
-rw-r--r--target/sparc/int32_helper.c2
-rw-r--r--target/sparc/int64_helper.c2
-rw-r--r--target/sparc/ldst_helper.c14
-rw-r--r--target/sparc/mmu_helper.c2
-rw-r--r--target/sparc/translate.c2
-rw-r--r--target/sparc/win_helper.c4
9 files changed, 238 insertions, 192 deletions
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index f63af728ee..af6d57a9e0 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -35,6 +35,7 @@
#define SPARC_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU)
+typedef struct sparc_def_t sparc_def_t;
/**
* SPARCCPUClass:
* @parent_realize: The parent class' realize handler.
@@ -49,6 +50,7 @@ typedef struct SPARCCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+ sparc_def_t *cpu_def;
} SPARCCPUClass;
typedef struct SPARCCPU SPARCCPU;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index d606eb53f4..0806d699e6 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -22,11 +22,11 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "exec/exec-all.h"
+#include "hw/qdev-properties.h"
+#include "qapi/visitor.h"
//#define DEBUG_FEATURES
-static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
-
/* CPUClass::reset() */
static void sparc_cpu_reset(CPUState *s)
{
@@ -68,7 +68,7 @@ static void sparc_cpu_reset(CPUState *s)
env->lsu = 0;
#else
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
- env->mmuregs[0] |= env->def->mmu_bm;
+ env->mmuregs[0] |= env->def.mmu_bm;
#endif
env->pc = 0;
env->npc = env->pc + 4;
@@ -104,62 +104,94 @@ static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
#endif
}
-static void sparc_cpu_parse_features(CPUState *cs, char *features,
- Error **errp);
+static void
+cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
+{
+ GlobalProperty *prop = g_new0(typeof(*prop), 1);
+ prop->driver = typename;
+ prop->property = g_strdup(name);
+ prop->value = g_strdup(val);
+ prop->errp = &error_fatal;
+ qdev_prop_register_global(prop);
+}
-static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
+/* Parse "+feature,-feature,feature=foo" CPU feature string */
+static void sparc_cpu_parse_features(const char *typename, char *features,
+ Error **errp)
{
- CPUSPARCState *env = &cpu->env;
- char *s = g_strdup(cpu_model);
- char *featurestr, *name = strtok(s, ",");
- sparc_def_t def1, *def = &def1;
- Error *err = NULL;
+ GList *l, *plus_features = NULL, *minus_features = NULL;
+ char *featurestr; /* Single 'key=value" string being parsed */
+ static bool cpu_globals_initialized;
- if (cpu_sparc_find_by_name(def, name) < 0) {
- g_free(s);
- return -1;
+ if (cpu_globals_initialized) {
+ return;
}
+ cpu_globals_initialized = true;
- env->def = g_memdup(def, sizeof(*def));
-
- featurestr = strtok(NULL, ",");
- sparc_cpu_parse_features(CPU(cpu), featurestr, &err);
- g_free(s);
- if (err) {
- error_report_err(err);
- return -1;
+ if (!features) {
+ return;
}
- env->version = def->iu_version;
- env->fsr = def->fpu_version;
- env->nwindows = def->nwindows;
-#if !defined(TARGET_SPARC64)
- env->mmuregs[0] |= def->mmu_version;
- cpu_sparc_set_id(env, 0);
- env->mxccregs[7] |= def->mxcc_version;
-#else
- env->mmu_version = def->mmu_version;
- env->maxtl = def->maxtl;
- env->version |= def->maxtl << 8;
- env->version |= def->nwindows - 1;
-#endif
- return 0;
-}
+ for (featurestr = strtok(features, ",");
+ featurestr;
+ featurestr = strtok(NULL, ",")) {
+ const char *name;
+ const char *val = NULL;
+ char *eq = NULL;
-SPARCCPU *cpu_sparc_init(const char *cpu_model)
-{
- SPARCCPU *cpu;
-
- cpu = SPARC_CPU(object_new(TYPE_SPARC_CPU));
+ /* Compatibility syntax: */
+ if (featurestr[0] == '+') {
+ plus_features = g_list_append(plus_features,
+ g_strdup(featurestr + 1));
+ continue;
+ } else if (featurestr[0] == '-') {
+ minus_features = g_list_append(minus_features,
+ g_strdup(featurestr + 1));
+ continue;
+ }
- if (cpu_sparc_register(cpu, cpu_model) < 0) {
- object_unref(OBJECT(cpu));
- return NULL;
+ eq = strchr(featurestr, '=');
+ name = featurestr;
+ if (eq) {
+ *eq++ = 0;
+ val = eq;
+
+ /*
+ * Temporarily, only +feat/-feat will be supported
+ * for boolean properties until we remove the
+ * minus-overrides-plus semantics and just follow
+ * the order options appear on the command-line.
+ *
+ * TODO: warn if user is relying on minus-override-plus semantics
+ * TODO: remove minus-override-plus semantics after
+ * warning for a few releases
+ */
+ if (!strcasecmp(val, "on") ||
+ !strcasecmp(val, "off") ||
+ !strcasecmp(val, "true") ||
+ !strcasecmp(val, "false")) {
+ error_setg(errp, "Boolean properties in format %s=%s"
+ " are not supported", name, val);
+ return;
+ }
+ } else {
+ error_setg(errp, "Unsupported property format: %s", name);
+ return;
+ }
+ cpu_add_feat_as_prop(typename, name, val);
}
- object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+ for (l = plus_features; l; l = l->next) {
+ const char *name = l->data;
+ cpu_add_feat_as_prop(typename, name, "on");
+ }
+ g_list_free_full(plus_features, g_free);
- return cpu;
+ for (l = minus_features; l; l = l->next) {
+ const char *name = l->data;
+ cpu_add_feat_as_prop(typename, name, "off");
+ }
+ g_list_free_full(minus_features, g_free);
}
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
@@ -540,124 +572,6 @@ static void print_features(FILE *f, fprintf_function cpu_fprintf,
}
}
-static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
- if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
- *features |= 1 << i;
- return;
- }
- }
- error_report("CPU feature %s not found", flagname);
-}
-
-static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *name)
-{
- unsigned int i;
- const sparc_def_t *def = NULL;
-
- for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
- if (strcasecmp(name, sparc_defs[i].name) == 0) {
- def = &sparc_defs[i];
- }
- }
- if (!def) {
- return -1;
- }
- memcpy(cpu_def, def, sizeof(*def));
- return 0;
-}
-
-static void sparc_cpu_parse_features(CPUState *cs, char *features,
- Error **errp)
-{
- SPARCCPU *cpu = SPARC_CPU(cs);
- sparc_def_t *cpu_def = cpu->env.def;
- char *featurestr;
- uint32_t plus_features = 0;
- uint32_t minus_features = 0;
- uint64_t iu_version;
- uint32_t fpu_version, mmu_version, nwindows;
-
- featurestr = features ? strtok(features, ",") : NULL;
- while (featurestr) {
- char *val;
-
- if (featurestr[0] == '+') {
- add_flagname_to_bitmaps(featurestr + 1, &plus_features);
- } else if (featurestr[0] == '-') {
- add_flagname_to_bitmaps(featurestr + 1, &minus_features);
- } else if ((val = strchr(featurestr, '='))) {
- *val = 0; val++;
- if (!strcmp(featurestr, "iu_version")) {
- char *err;
-
- iu_version = strtoll(val, &err, 0);
- if (!*val || *err) {
- error_setg(errp, "bad numerical value %s", val);
- return;
- }
- cpu_def->iu_version = iu_version;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
-#endif
- } else if (!strcmp(featurestr, "fpu_version")) {
- char *err;
-
- fpu_version = strtol(val, &err, 0);
- if (!*val || *err) {
- error_setg(errp, "bad numerical value %s", val);
- return;
- }
- cpu_def->fpu_version = fpu_version;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "fpu_version %x\n", fpu_version);
-#endif
- } else if (!strcmp(featurestr, "mmu_version")) {
- char *err;
-
- mmu_version = strtol(val, &err, 0);
- if (!*val || *err) {
- error_setg(errp, "bad numerical value %s", val);
- return;
- }
- cpu_def->mmu_version = mmu_version;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "mmu_version %x\n", mmu_version);
-#endif
- } else if (!strcmp(featurestr, "nwindows")) {
- char *err;
-
- nwindows = strtol(val, &err, 0);
- if (!*val || *err || nwindows > MAX_NWINDOWS ||
- nwindows < MIN_NWINDOWS) {
- error_setg(errp, "bad numerical value %s", val);
- return;
- }
- cpu_def->nwindows = nwindows;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "nwindows %d\n", nwindows);
-#endif
- } else {
- error_setg(errp, "unrecognized feature %s", featurestr);
- return;
- }
- } else {
- error_setg(errp, "feature string `%s' not in format "
- "(+feature|-feature|feature=xyz)", featurestr);
- return;
- }
- featurestr = strtok(NULL, ",");
- }
- cpu_def->features |= plus_features;
- cpu_def->features &= ~minus_features;
-#ifdef DEBUG_FEATURES
- print_features(stderr, fprintf, cpu_def->features, NULL);
-#endif
-}
-
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
unsigned int i;
@@ -796,20 +710,64 @@ static bool sparc_cpu_has_work(CPUState *cs)
cpu_interrupts_enabled(env);
}
+static char *sparc_cpu_type_name(const char *cpu_model)
+{
+ char *name = g_strdup_printf("%s-" TYPE_SPARC_CPU, cpu_model);
+ char *s = name;
+
+ /* SPARC cpu model names happen to have whitespaces,
+ * as type names shouldn't have spaces replace them with '-'
+ */
+ while ((s = strchr(s, ' '))) {
+ *s = '-';
+ }
+
+ return name;
+}
+
+static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc;
+ char *typename;
+
+ if (cpu_model == NULL) {
+ return NULL;
+ }
+
+ typename = sparc_cpu_type_name(cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ return oc;
+}
+
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
Error *local_err = NULL;
-#if defined(CONFIG_USER_ONLY)
SPARCCPU *cpu = SPARC_CPU(dev);
CPUSPARCState *env = &cpu->env;
- if ((env->def->features & CPU_FEATURE_FLOAT)) {
- env->def->features |= CPU_FEATURE_FLOAT128;
+#if defined(CONFIG_USER_ONLY)
+ if ((env->def.features & CPU_FEATURE_FLOAT)) {
+ env->def.features |= CPU_FEATURE_FLOAT128;
}
#endif
+ env->version = env->def.iu_version;
+ env->fsr = env->def.fpu_version;
+ env->nwindows = env->def.nwindows;
+#if !defined(TARGET_SPARC64)
+ env->mmuregs[0] |= env->def.mmu_version;
+ cpu_sparc_set_id(env, 0);
+ env->mxccregs[7] |= env->def.mxcc_version;
+#else
+ env->mmu_version = env->def.mmu_version;
+ env->maxtl = env->def.maxtl;
+ env->version |= env->def.maxtl << 8;
+ env->version |= env->def.nwindows - 1;
+#endif
+
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -825,6 +783,7 @@ static void sparc_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
SPARCCPU *cpu = SPARC_CPU(obj);
+ SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
CPUSPARCState *env = &cpu->env;
cs->env_ptr = env;
@@ -832,16 +791,75 @@ static void sparc_cpu_initfn(Object *obj)
if (tcg_enabled()) {
gen_intermediate_code_init(env);
}
+
+ if (scc->cpu_def) {
+ env->def = *scc->cpu_def;
+ }
}
-static void sparc_cpu_uninitfn(Object *obj)
+static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
SPARCCPU *cpu = SPARC_CPU(obj);
- CPUSPARCState *env = &cpu->env;
+ int64_t value = cpu->env.def.nwindows;
+
+ visit_type_int(v, name, &value, errp);
+}
+
+static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const int64_t min = MIN_NWINDOWS;
+ const int64_t max = MAX_NWINDOWS;
+ SPARCCPU *cpu = SPARC_CPU(obj);
+ Error *err = NULL;
+ int64_t value;
- g_free(env->def);
+ visit_type_int(v, name, &value, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ if (value < min || value > max) {
+ error_setg(errp, "Property %s.%s doesn't take value %" PRId64
+ " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
+ object_get_typename(obj), name ? name : "null",
+ value, min, max);
+ return;
+ }
+ cpu->env.def.nwindows = value;
}
+static PropertyInfo qdev_prop_nwindows = {
+ .name = "int",
+ .get = sparc_get_nwindows,
+ .set = sparc_set_nwindows,
+};
+
+static Property sparc_cpu_properties[] = {
+ DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false),
+ DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
+ DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false),
+ DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false),
+ DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false),
+ DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false),
+ DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false),
+ DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false),
+ DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false),
+ DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false),
+ DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false),
+ DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false),
+ DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false),
+ DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false),
+ DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
+ qdev_prop_uint64, target_ulong),
+ DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
+ DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
+ { .name = "nwindows", .info = &qdev_prop_nwindows },
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
{
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
@@ -850,10 +868,13 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
scc->parent_realize = dc->realize;
dc->realize = sparc_cpu_realizefn;
+ dc->props = sparc_cpu_properties;
scc->parent_reset = cc->reset;
cc->reset = sparc_cpu_reset;
+ cc->class_by_name = sparc_cpu_class_by_name;
+ cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
@@ -887,15 +908,39 @@ static const TypeInfo sparc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(SPARCCPU),
.instance_init = sparc_cpu_initfn,
- .instance_finalize = sparc_cpu_uninitfn,
- .abstract = false,
+ .abstract = true,
.class_size = sizeof(SPARCCPUClass),
.class_init = sparc_cpu_class_init,
};
+static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
+{
+ SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
+ scc->cpu_def = data;
+}
+
+static void sparc_register_cpudef_type(const struct sparc_def_t *def)
+{
+ char *typename = sparc_cpu_type_name(def->name);
+ TypeInfo ti = {
+ .name = typename,
+ .parent = TYPE_SPARC_CPU,
+ .class_init = sparc_cpu_cpudef_class_init,
+ .class_data = (void *)def,
+ };
+
+ type_register(&ti);
+ g_free(typename);
+}
+
static void sparc_cpu_register_types(void)
{
+ int i;
+
type_register_static(&sparc_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
+ sparc_register_cpudef_type(&sparc_defs[i]);
+ }
}
type_init(sparc_cpu_register_types)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 95a36a4bdc..b45cfb4708 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -529,7 +529,7 @@ struct CPUSPARCState {
#define SOFTINT_INTRMASK (0xFFFE)
#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
#endif
- sparc_def_t *def;
+ sparc_def_t def;
void *irq_manager;
void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
@@ -579,7 +579,6 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
#ifndef NO_CPU_IO_DEFS
/* cpu_init.c */
-SPARCCPU *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
/* mmu_helper.c */
@@ -656,7 +655,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#ifndef NO_CPU_IO_DEFS
-#define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model))
+#define cpu_init(cpu_model) cpu_generic_init(TYPE_SPARC_CPU, cpu_model)
#endif
#define cpu_signal_handler cpu_sparc_signal_handler
@@ -679,7 +678,7 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#if defined (TARGET_SPARC64)
static inline int cpu_has_hypervisor(CPUSPARCState *env1)
{
- return env1->def->features & CPU_FEATURE_HYPV;
+ return env1->def.features & CPU_FEATURE_HYPV;
}
static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
@@ -788,14 +787,14 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
if (env->pstate & PS_AM) {
flags |= TB_FLAG_AM_ENABLED;
}
- if ((env->def->features & CPU_FEATURE_FLOAT)
+ if ((env->def.features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED;
}
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
- if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
+ if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
flags |= TB_FLAG_FPU_ENABLED;
}
#endif
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index eec9a4d49f..c7724928c0 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -108,7 +108,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
if (cs->exception_index == 0x80 &&
- env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
+ env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
} else {
cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index f942973c22..f3e7f32de6 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -147,7 +147,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
}
}
- if (env->def->features & CPU_FEATURE_GL) {
+ if (env->def.features & CPU_FEATURE_GL) {
tsptr->tstate |= (env->gl & 7ULL) << 40;
cpu_gl_switch_gregs(env, env->gl + 1);
env->gl++;
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 57968d9143..fb489cb5fd 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -513,7 +513,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
ret = leon3_cache_control_ld(env, addr, size);
}
break;
@@ -736,7 +736,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
leon3_cache_control_st(env, addr, val, size);
}
break;
@@ -904,15 +904,15 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
/* Mappings generated during no-fault mode
are invalid in normal mode. */
if ((oldreg ^ env->mmuregs[reg])
- & (MMU_NF | env->def->mmu_bm)) {
+ & (MMU_NF | env->def.mmu_bm)) {
tlb_flush(CPU(cpu));
}
break;
case 1: /* Context Table Pointer Register */
- env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
+ env->mmuregs[reg] = val & env->def.mmu_ctpr_mask;
break;
case 2: /* Context Register */
- env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
+ env->mmuregs[reg] = val & env->def.mmu_cxr_mask;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
@@ -923,11 +923,11 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 4: /* Synchronous Fault Address Register */
break;
case 0x10: /* TLB Replacement Control Register */
- env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
+ env->mmuregs[reg] = val & env->def.mmu_trcr_mask;
break;
case 0x13: /* Synchronous Fault Status Register with Read
and Clear */
- env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
+ env->mmuregs[3] = val & env->def.mmu_sfsr_mask;
break;
case 0x14: /* Synchronous Fault Address Register */
env->mmuregs[4] = val;
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 8b4664d996..126ea5e3ee 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -95,7 +95,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
if (mmu_idx == MMU_PHYS_IDX) {
*page_size = TARGET_PAGE_SIZE;
/* Boot mode: instruction fetches are taken from PROM */
- if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
+ if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) {
*physical = env->prom_addr | (address & 0x7ffffULL);
*prot = PAGE_READ | PAGE_EXEC;
return 0;
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 3bde47be83..6290705b11 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5756,7 +5756,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
- dc->def = env->def;
+ dc->def = &env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (cs->singlestep_enabled || singlestep);
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index 154279ecda..8290a21142 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -295,7 +295,7 @@ void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
{
- if (env->def->features & CPU_FEATURE_GL) {
+ if (env->def.features & CPU_FEATURE_GL) {
return env->glregs + (env->gl & 7) * 8;
}
@@ -343,7 +343,7 @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
uint32_t pstate_regs, new_pstate_regs;
uint64_t *src, *dst;
- if (env->def->features & CPU_FEATURE_GL) {
+ if (env->def.features & CPU_FEATURE_GL) {
/* PS_AG, IG and MG are not implemented in this case */
new_pstate &= ~(PS_AG | PS_IG | PS_MG);
env->pstate = new_pstate;
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-23 00:51:18 +0200