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-rw-r--r--target/loongarch/cpu.c1
-rw-r--r--target/loongarch/tlb_helper.c5
2 files changed, 4 insertions, 2 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b28aaed5ba..1512664214 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -177,6 +177,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
}
QEMU_FALLTHROUGH;
case EXCCODE_PIF:
+ case EXCCODE_ADEF:
cause = cs->exception_index;
update_badinstr = 0;
break;
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 610b6d123c..d2f8fb0c60 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -229,7 +229,8 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
switch (tlb_error) {
default:
case TLBRET_BADADDR:
- cs->exception_index = EXCCODE_ADEM;
+ cs->exception_index = access_type == MMU_INST_FETCH
+ ? EXCCODE_ADEF : EXCCODE_ADEM;
break;
case TLBRET_NOMATCH:
/* No TLB match for a mapped address */
@@ -643,7 +644,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPULoongArchState *env = &cpu->env;
hwaddr physical;
int prot;
- int ret = TLBRET_BADADDR;
+ int ret;
/* Data access */
ret = get_physical_address(env, &physical, &prot, address,