diff options
Diffstat (limited to 'tcg/aarch64/tcg-target.c.inc')
| -rw-r--r-- | tcg/aarch64/tcg-target.c.inc | 88 |
1 files changed, 29 insertions, 59 deletions
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 42037c98fa..3c1ee39fd4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2547,42 +2547,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, va_end(va); } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } }; - static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } }; - static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; - static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } }; - static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; - static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; - static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } }; - static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } }; - static const TCGTargetOpDef r_r_rAL - = { .args_ct_str = { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - = { .args_ct_str = { "w", "w", "w", "w" } }; - +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) +{ switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -2621,7 +2590,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: - return &r_r; + return C_O1_I1(r, r); case INDEX_op_st8_i32: case INDEX_op_st16_i32: @@ -2630,7 +2599,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st16_i64: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &rZ_r; + return C_O0_I2(rZ, r); case INDEX_op_add_i32: case INDEX_op_add_i64: @@ -2638,7 +2607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return &r_r_rA; + return C_O1_I2(r, r, rA); case INDEX_op_mul_i32: case INDEX_op_mul_i64: @@ -2652,7 +2621,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_remu_i64: case INDEX_op_muluh_i64: case INDEX_op_mulsh_i64: - return &r_r_r; + return C_O1_I2(r, r, r); case INDEX_op_and_i32: case INDEX_op_and_i64: @@ -2666,7 +2635,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return &r_r_rL; + return C_O1_I2(r, r, rL); case INDEX_op_shl_i32: case INDEX_op_shr_i32: @@ -2678,42 +2647,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: - return &r_r_ri; + return C_O1_I2(r, r, ri); case INDEX_op_clz_i32: case INDEX_op_ctz_i32: case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - return &r_r_rAL; + return C_O1_I2(r, r, rAL); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_rA; + return C_O0_I2(r, rA); case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return &movc; + return C_O1_I4(r, r, rA, rZ, rZ); case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_l; + return C_O1_I1(r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return &lZ_l; + return C_O0_I2(lZ, l); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return &dep; + return C_O1_I2(r, 0, rZ); case INDEX_op_extract2_i32: case INDEX_op_extract2_i64: - return &ext2; + return C_O1_I2(r, rZ, rZ); case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: case INDEX_op_sub2_i64: - return &add2; + return C_O2_I4(r, r, rZ, rZ, rA, rMZ); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2731,35 +2700,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: case INDEX_op_aa64_sshl_vec: - return &w_w_w; + return C_O1_I2(w, w, w); case INDEX_op_not_vec: case INDEX_op_neg_vec: case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: - return &w_w; + return C_O1_I1(w, w); case INDEX_op_ld_vec: - case INDEX_op_st_vec: case INDEX_op_dupm_vec: - return &w_r; + return C_O1_I1(w, r); + case INDEX_op_st_vec: + return C_O0_I2(w, r); case INDEX_op_dup_vec: - return &w_wr; + return C_O1_I1(w, wr); case INDEX_op_or_vec: case INDEX_op_andc_vec: - return &w_w_wO; + return C_O1_I2(w, w, wO); case INDEX_op_and_vec: case INDEX_op_orc_vec: - return &w_w_wN; + return C_O1_I2(w, w, wN); case INDEX_op_cmp_vec: - return &w_w_wZ; + return C_O1_I2(w, w, wZ); case INDEX_op_bitsel_vec: - return &w_w_w_w; + return C_O1_I3(w, w, w, w); case INDEX_op_aa64_sli_vec: - return &w_0_w; + return C_O1_I2(w, 0, w); default: - return NULL; + g_assert_not_reached(); } } |