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-rwxr-xr-xtests/tcg/configure.sh4
-rw-r--r--tests/tcg/ppc64le/bcdsub.c144
-rw-r--r--tests/tcg/ppc64le/mtfsf.c19
-rw-r--r--tests/tcg/ppc64le/non_signalling_xscv.c16
4 files changed, 93 insertions, 90 deletions
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 0663bd19f4..ed4b5ccb1f 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -64,9 +64,9 @@ fi
: ${cross_cc_ppc="powerpc-linux-gnu-gcc"}
: ${cross_cc_cflags_ppc="-m32"}
: ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"}
-: ${cross_cc_cflags_ppc64="-m64 -mbig"}
+: ${cross_cc_cflags_ppc64="-m64 -mbig-endian"}
: ${cross_cc_ppc64le="$cross_cc_ppc64"}
-: ${cross_cc_cflags_ppc64le="-m64 -mlittle"}
+: ${cross_cc_cflags_ppc64le="-m64 -mlittle-endian"}
: ${cross_cc_riscv64="riscv64-linux-gnu-gcc"}
: ${cross_cc_s390x="s390x-linux-gnu-gcc"}
: ${cross_cc_sh4="sh4-linux-gnu-gcc"}
diff --git a/tests/tcg/ppc64le/bcdsub.c b/tests/tcg/ppc64le/bcdsub.c
index 8c188cae6d..87c8c44a44 100644
--- a/tests/tcg/ppc64le/bcdsub.c
+++ b/tests/tcg/ppc64le/bcdsub.c
@@ -1,6 +1,7 @@
#include <assert.h>
#include <unistd.h>
#include <signal.h>
+#include <stdint.h>
#define CRF_LT (1 << 3)
#define CRF_GT (1 << 2)
@@ -8,24 +9,50 @@
#define CRF_SO (1 << 0)
#define UNDEF 0
-#define BCDSUB(vra, vrb, ps) \
- asm ("bcdsub. %1,%2,%3,%4;" \
- "mfocrf %0,0b10;" \
- : "=r" (cr), "=v" (vrt) \
- : "v" (vra), "v" (vrb), "i" (ps) \
- : );
-
-#define TEST(vra, vrb, ps, exp_res, exp_cr6) \
- do { \
- __int128 vrt = 0; \
- int cr = 0; \
- BCDSUB(vra, vrb, ps); \
- if (exp_res) \
- assert(vrt == exp_res); \
- assert((cr >> 4) == exp_cr6); \
+#ifdef __has_builtin
+#if !__has_builtin(__builtin_bcdsub)
+#define NO_BUILTIN_BCDSUB
+#endif
+#endif
+
+#ifdef NO_BUILTIN_BCDSUB
+#define BCDSUB(T, A, B, PS) \
+ ".long 4 << 26 | (" #T ") << 21 | (" #A ") << 16 | (" #B ") << 11" \
+ " | 1 << 10 | (" #PS ") << 9 | 65\n\t"
+#else
+#define BCDSUB(T, A, B, PS) "bcdsub. " #T ", " #A ", " #B ", " #PS "\n\t"
+#endif
+
+#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \
+ do { \
+ int cr = 0; \
+ uint64_t th, tl; \
+ /* \
+ * Use GPR pairs to load the VSR values and place the resulting VSR and\
+ * CR6 in th, tl, and cr. Note that we avoid newer instructions (e.g., \
+ * mtvsrdd/mfvsrld) so we can run this test on POWER8 machines. \
+ */ \
+ asm ("mtvsrd 32, %3\n\t" \
+ "mtvsrd 33, %4\n\t" \
+ "xxmrghd 32, 32, 33\n\t" \
+ "mtvsrd 33, %5\n\t" \
+ "mtvsrd 34, %6\n\t" \
+ "xxmrghd 33, 33, 34\n\t" \
+ BCDSUB(0, 0, 1, PS) \
+ "mfocrf %0, 0b10\n\t" \
+ "mfvsrd %1, 32\n\t" \
+ "xxswapd 32, 32\n\t" \
+ "mfvsrd %2, 32\n\t" \
+ : "=r" (cr), "=r" (th), "=r" (tl) \
+ : "r" (AH), "r" (AL), "r" (BH), "r" (BL) \
+ : "v0", "v1", "v2"); \
+ if (TH != UNDEF || TL != UNDEF) { \
+ assert(tl == TL); \
+ assert(th == TH); \
+ } \
+ assert((cr >> 4) == CR6); \
} while (0)
-
/*
* Unbounded result is equal to zero:
* sign = (PS) ? 0b1111 : 0b1100
@@ -33,13 +60,13 @@
*/
void test_bcdsub_eq(void)
{
- __int128 a, b;
-
/* maximum positive BCD value */
- a = b = (((__int128) 0x9999999999999999) << 64 | 0x999999999999999c);
-
- TEST(a, b, 0, 0xc, CRF_EQ);
- TEST(a, b, 1, 0xf, CRF_EQ);
+ TEST(0x9999999999999999, 0x999999999999999c,
+ 0x9999999999999999, 0x999999999999999c,
+ 0, 0x0, 0xc, CRF_EQ);
+ TEST(0x9999999999999999, 0x999999999999999c,
+ 0x9999999999999999, 0x999999999999999c,
+ 1, 0x0, 0xf, CRF_EQ);
}
/*
@@ -49,21 +76,16 @@ void test_bcdsub_eq(void)
*/
void test_bcdsub_gt(void)
{
- __int128 a, b, c;
-
- /* maximum positive BCD value */
- a = (((__int128) 0x9999999999999999) << 64 | 0x999999999999999c);
-
- /* negative one BCD value */
- b = (__int128) 0x1d;
-
- TEST(a, b, 0, 0xc, (CRF_GT | CRF_SO));
- TEST(a, b, 1, 0xf, (CRF_GT | CRF_SO));
-
- c = (((__int128) 0x9999999999999999) << 64 | 0x999999999999998c);
-
- TEST(c, b, 0, a, CRF_GT);
- TEST(c, b, 1, (a | 0x3), CRF_GT);
+ /* maximum positive and negative one BCD values */
+ TEST(0x9999999999999999, 0x999999999999999c, 0x0, 0x1d, 0,
+ 0x0, 0xc, (CRF_GT | CRF_SO));
+ TEST(0x9999999999999999, 0x999999999999999c, 0x0, 0x1d, 1,
+ 0x0, 0xf, (CRF_GT | CRF_SO));
+
+ TEST(0x9999999999999999, 0x999999999999998c, 0x0, 0x1d, 0,
+ 0x9999999999999999, 0x999999999999999c, CRF_GT);
+ TEST(0x9999999999999999, 0x999999999999998c, 0x0, 0x1d, 1,
+ 0x9999999999999999, 0x999999999999999f, CRF_GT);
}
/*
@@ -73,45 +95,27 @@ void test_bcdsub_gt(void)
*/
void test_bcdsub_lt(void)
{
- __int128 a, b;
-
- /* positive zero BCD value */
- a = (__int128) 0xc;
-
- /* positive one BCD value */
- b = (__int128) 0x1c;
-
- TEST(a, b, 0, 0x1d, CRF_LT);
- TEST(a, b, 1, 0x1d, CRF_LT);
-
- /* maximum negative BCD value */
- a = (((__int128) 0x9999999999999999) << 64 | 0x999999999999999d);
-
- /* positive one BCD value */
- b = (__int128) 0x1c;
-
- TEST(a, b, 0, 0xd, (CRF_LT | CRF_SO));
- TEST(a, b, 1, 0xd, (CRF_LT | CRF_SO));
+ /* positive zero and positive one BCD values */
+ TEST(0x0, 0xc, 0x0, 0x1c, 0, 0x0, 0x1d, CRF_LT);
+ TEST(0x0, 0xc, 0x0, 0x1c, 1, 0x0, 0x1d, CRF_LT);
+
+ /* maximum negative and positive one BCD values */
+ TEST(0x9999999999999999, 0x999999999999999d, 0x0, 0x1c, 0,
+ 0x0, 0xd, (CRF_LT | CRF_SO));
+ TEST(0x9999999999999999, 0x999999999999999d, 0x0, 0x1c, 1,
+ 0x0, 0xd, (CRF_LT | CRF_SO));
}
void test_bcdsub_invalid(void)
{
- __int128 a, b;
-
- /* positive one BCD value */
- a = (__int128) 0x1c;
- b = 0xf00;
-
- TEST(a, b, 0, UNDEF, CRF_SO);
- TEST(a, b, 1, UNDEF, CRF_SO);
-
- TEST(b, a, 0, UNDEF, CRF_SO);
- TEST(b, a, 1, UNDEF, CRF_SO);
+ TEST(0x0, 0x1c, 0x0, 0xf00, 0, UNDEF, UNDEF, CRF_SO);
+ TEST(0x0, 0x1c, 0x0, 0xf00, 1, UNDEF, UNDEF, CRF_SO);
- a = 0xbad;
+ TEST(0x0, 0xf00, 0x0, 0x1c, 0, UNDEF, UNDEF, CRF_SO);
+ TEST(0x0, 0xf00, 0x0, 0x1c, 1, UNDEF, UNDEF, CRF_SO);
- TEST(a, b, 0, UNDEF, CRF_SO);
- TEST(a, b, 1, UNDEF, CRF_SO);
+ TEST(0x0, 0xbad, 0x0, 0xf00, 0, UNDEF, UNDEF, CRF_SO);
+ TEST(0x0, 0xbad, 0x0, 0xf00, 1, UNDEF, UNDEF, CRF_SO);
}
int main(void)
diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c
index b3d31f3637..bed5b1afa4 100644
--- a/tests/tcg/ppc64le/mtfsf.c
+++ b/tests/tcg/ppc64le/mtfsf.c
@@ -1,8 +1,12 @@
#include <stdlib.h>
+#include <stdint.h>
#include <assert.h>
#include <signal.h>
#include <sys/prctl.h>
+#define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FRB))
+#define MFFS(FRT) asm("mffs %0" : "=f" (FRT))
+
#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
#define FPSCR_FI 17 /* Floating-point fraction inexact */
@@ -21,10 +25,7 @@ void sigfpe_handler(int sig, siginfo_t *si, void *ucontext)
int main(void)
{
- union {
- double d;
- long long ll;
- } fpscr;
+ uint64_t fpscr;
struct sigaction sa = {
.sa_sigaction = sigfpe_handler,
@@ -40,10 +41,9 @@ int main(void)
prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE);
/* First test if the FI bit is being set correctly */
- fpscr.ll = FP_FI;
- __builtin_mtfsf(0b11111111, fpscr.d);
- fpscr.d = __builtin_mffs();
- assert((fpscr.ll & FP_FI) != 0);
+ MTFSF(0b11111111, FP_FI);
+ MFFS(fpscr);
+ assert((fpscr & FP_FI) != 0);
/* Then test if the deferred exception is being called correctly */
sigaction(SIGFPE, &sa, NULL);
@@ -54,8 +54,7 @@ int main(void)
* But if a different exception is chosen si_code check should
* change accordingly.
*/
- fpscr.ll = FP_VE | FP_VXSOFT;
- __builtin_mtfsf(0b11111111, fpscr.d);
+ MTFSF(0b11111111, FP_VE | FP_VXSOFT);
return 1;
}
diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/non_signalling_xscv.c
index 91e25cad46..836df71ef0 100644
--- a/tests/tcg/ppc64le/non_signalling_xscv.c
+++ b/tests/tcg/ppc64le/non_signalling_xscv.c
@@ -6,16 +6,16 @@
#define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \
do { \
uint64_t th, tl, bh = B_HI, bl = B_LO; \
- asm("mtvsrd 0, %2\n\t" \
- "mtvsrd 1, %3\n\t" \
- "xxmrghd 0, 0, 1\n\t" \
- INSN " 0, 0\n\t" \
- "mfvsrd %0, 0\n\t" \
- "xxswapd 0, 0\n\t" \
- "mfvsrd %1, 0\n\t" \
+ asm("mtvsrd 32, %2\n\t" \
+ "mtvsrd 33, %3\n\t" \
+ "xxmrghd 32, 32, 33\n\t" \
+ INSN " 32, 32\n\t" \
+ "mfvsrd %0, 32\n\t" \
+ "xxswapd 32, 32\n\t" \
+ "mfvsrd %1, 32\n\t" \
: "=r" (th), "=r" (tl) \
: "r" (bh), "r" (bl) \
- : "vs0", "vs1"); \
+ : "v0", "v1"); \
printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \
"%016" PRIx64 "\n", bh, bl, th, tl); \
assert(th == T_HI && tl == T_LO); \
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 03:14:48 +0100