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* migrate/ram: remove "ram_bulk_stage" and "fpo_enabled"David Hildenbrand2021-05-134-68/+18Star
* Merge remote-tracking branch 'remotes/philmd/tags/pflash-20210511' into stagingPeter Maydell2021-05-131-3/+7
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| * hw/block/pflash_cfi02: Do not create aliases when not necessaryPhilippe Mathieu-Daudé2021-05-111-2/+6
| * hw/block/pflash_cfi02: Set romd mode in pflash_cfi02_realize()Philippe Mathieu-Daudé2021-05-111-1/+1
* | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell2021-05-1247-789/+1759
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| * | target/riscv: Fix the RV64H decode commentAlistair Francis2021-05-111-1/+1
| * | target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-115-72/+39Star
| * | target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-1114-150/+166
| * | target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis2021-05-111-6/+0Star
| * | target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis2021-05-111-6/+0Star
| * | target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-114-28/+56
| * | target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-113-14/+27
| * | target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-112-20/+15Star
| * | target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-112-7/+8
| * | target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-112-7/+5Star
| * | target/riscv: fix a typo with interrupt namesEmmanuel Blot2021-05-111-1/+1
| * | fpu/softfloat: set invalid excp flag for RISC-V muladd instructionsFrank Chang2021-05-111-0/+6
| * | hw/riscv: Fix OT IBEX reset vectorAlexander Wagner2021-05-111-1/+1
| * | target/riscv: fix exception index on instruction access faultEmmanuel Blot2021-05-111-1/+3
| * | target/riscv: fix vrgather macro index variable type bugFrank Chang2021-05-111-2/+4
| * | target/riscv: Add ePMP support for the Ibex CPUAlistair Francis2021-05-111-0/+1
| * | target/riscv/pmp: Remove outdated commentAlistair Francis2021-05-111-4/+0Star
| * | target/riscv: Add a config option for ePMPHou Weiying2021-05-112-0/+11
| * | target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying2021-05-111-8/+146
| * | target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-115-0/+76
| * | target/riscv: Add the ePMP featureAlistair Francis2021-05-111-0/+1
| * | target/riscv: Define ePMP mseccfgHou Weiying2021-05-111-0/+3
| * | target/riscv: Fix the PMP is locked check when using TORAlistair Francis2021-05-111-10/+16
| * | docs: Add documentation for shakti_c machineVijai Kumar K2021-05-112-0/+83
| * | target/riscv: Fixup saturate subtract functionLIU Zhiwei2021-05-111-4/+4
| * | riscv: don't look at SUM when accessing memory from a debugger contextJade Fink2021-05-111-8/+12
| * | hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis2021-05-111-0/+1
| * | hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-113-22/+22
| * | MAINTAINERS: Update the RISC-V CPU MaintainersAlistair Francis2021-05-111-3/+2Star
| * | target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-114-36/+38
| * | target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-112-261/+382
| * | target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis2021-05-111-1/+5
| * | target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-112-37/+46
| * | target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-113-24/+26
| * | hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K2021-05-112-0/+10
| * | hw/char: Add Shakti UART emulationVijai Kumar K2021-05-115-0/+266
| * | riscv: Add initial support for Shakti C machineVijai Kumar K2021-05-116-0/+265
| * | target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-112-0/+2
| * | hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng2021-05-111-1/+1
| * | target/riscv: Align the data type of reset vector addressDylan Jhong2021-05-111-1/+1
| * | docs/system/generic-loader.rst: Fix styleAxel Heider2021-05-111-3/+6
| * | target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-117-72/+23Star
* | | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-05-1259-2674/+3299
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| * | | coverity-scan: list components, move model to scripts/coverity-scanPaolo Bonzini2021-05-122-0/+154
| * | | configure: fix detection of gdbus-codegenPaolo Bonzini2021-05-121-1/+3
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