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* target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens2019-05-241-1/+3
* target/riscv: More accurate handling of `sip` CSRJonathan Behrens2019-05-241-2/+5
* target/riscv: Add checks for several RVC reserved operandsRichard Henderson2019-05-242-3/+14
* target/riscv: Add the HGATP register masksAlistair Francis2019-05-241-0/+11
* target/riscv: Add the HSTATUS register masksAlistair Francis2019-05-241-0/+18
* target/riscv: Add Hypervisor CSR macrosAlistair Francis2019-05-241-3/+6
* target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis2019-05-241-9/+8Star
* target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis2019-05-241-3/+2Star
* target/riscv: Improve the scause logicAlistair Francis2019-05-241-1/+1
* target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2019-05-242-8/+27
* target/riscv: Mark privilege level 2 as reservedAlistair Francis2019-05-241-1/+1
* riscv: spike: Add a generic spike machineAlistair Francis2019-05-242-1/+111
* target/riscv: Deprecate the generic no MMU CPUsAlistair Francis2019-05-241-0/+6
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-244-2/+27
* target/riscv: Create settable CPU propertiesAlistair Francis2019-05-242-0/+57
* riscv: virt: Allow specifying a CPU via commandlineAlistair Francis2019-05-241-1/+2
* linux-user/riscv: Add the CPU type as a commentAlistair Francis2019-05-241-0/+1
* target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens2019-05-241-1/+0Star
* target/riscv: Remove spaces from register namesRichard Henderson2019-05-241-8/+8
* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-242-9/+24
* target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-246-151/+67Star
* target/riscv: Use pattern groups in insn16.decodeRichard Henderson2019-05-243-69/+29Star
* target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-243-53/+12Star
* target/riscv: Merge argument sets for insn32 and insn16Richard Henderson2019-05-242-170/+58Star
* target/riscv: Use --static-decode for decodetreeRichard Henderson2019-05-242-7/+4Star
* target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-242-3/+25
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-243-12/+32
* target/riscv: Do not allow sfence.vma from user modeJonathan Behrens2019-05-241-3/+4
* SiFive RISC-V GPIO DeviceFabien Chouteau2019-05-247-4/+501
* Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-4.1-pull-re...Peter Maydell2019-05-246-62/+143
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| * linux-user: Pass through nanosecond timestamp components for stat syscallsChen-Yu Tsai2019-05-242-18/+50
| * linux-user: Align mmap_find_vma to host page sizeRichard Henderson2019-05-241-0/+2
| * linux-user: Fix shmat emulation by honoring host SHMLBARichard Henderson2019-05-244-42/+50
| * linux-user: Sanitize interp_info and, for mips only, init field fp_abiDaniel Santos2019-05-221-0/+5
| * linux-user: Add support for SIOC<G|S>IFPFLAGS ioctls for all targetsNeng Chen2019-05-222-0/+4
| * linux-user: Add support for SIOCSPGRP ioctl for all targetsAleksandar Markovic2019-05-222-0/+4
| * linux-user: Fix support for SIOCATMARK and SIOCGPGRP ioctls for xtensaAleksandar Markovic2019-05-221-1/+2
| * linux-user: add pseudo /proc/hardware for m68kLaurent Vivier2019-05-221-1/+12
| * linux-user: add pseudo /proc/cpuinfo for sparcLaurent Vivier2019-05-221-1/+15
* | Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190524-pull-request' ...Peter Maydell2019-05-245-21/+88
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| * | hw/display/ramfb: initialize fw-config space with xres/ yresHou Qiming2019-05-245-6/+30
| * | hw/display/ramfb: lock guest resolution after it's setHou Qiming2019-05-241-4/+22
| * | hw/display/ramfb: fix guest memory un-mappingHou Qiming2019-05-241-13/+38
* | | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190522' into stagingPeter Maydell2019-05-2414-187/+619
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| * | | tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/storeRichard Henderson2019-05-221-2/+22
| * | | tcg/aarch64: Allow immediates for vector ORR and BICRichard Henderson2019-05-221-7/+83
| * | | tcg/aarch64: Build vector immediates with two insnsRichard Henderson2019-05-221-0/+47
| * | | tcg/aarch64: Use MVNI in tcg_out_dupi_vecRichard Henderson2019-05-221-0/+11
| * | | tcg/aarch64: Split up is_fimmRichard Henderson2019-05-221-84/+119
| * | | tcg/aarch64: Support vector bitwise select valueRichard Henderson2019-05-222-2/+24