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| * | | target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis2019-09-171-1/+1
| * | | target/riscv: Fix mstatus dirty maskAlistair Francis2019-09-171-1/+1
| * | | target/riscv: Use both register name and ABI nameAtish Patra2019-09-171-8/+11
| * | | riscv: sifive_u: Update model and compatible strings in device treeBin Meng2019-09-171-2/+3
| * | | riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-172-25/+2Star
| * | | riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-173-5/+23
| * | | riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-172-0/+12
| * | | riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-173-0/+272
| * | | riscv: roms: Update default bios for sifive_u machineBin Meng2019-09-172-2/+2
| * | | riscv: sifive_u: Change UART node name in device treeBin Meng2019-09-171-1/+1
| * | | riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-172-4/+4
| * | | riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-172-3/+14
| * | | riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-172-1/+26
| * | | riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-172-0/+25
| * | | riscv: sifive: Implement PRCI model for FU540Bin Meng2019-09-173-0/+251
| * | | riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng2019-09-171-3/+4
| * | | riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-172-26/+72
| * | | riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-172-1/+6
| * | | riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2019-09-172-1/+3
| * | | riscv: hart: Extract hart realize to a separate routineBin Meng2019-09-171-13/+20
| * | | riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng2019-09-173-12/+33
| * | | riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2019-09-172-15/+9Star
| * | | riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2019-09-172-1/+3
| * | | riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng2019-09-171-1/+1
| * | | riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng2019-09-175-114/+111Star
| * | | riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng2019-09-171-1/+0Star
| * | | riscv: roms: Remove executable attribute of opensbi imagesBin Meng2019-09-173-0/+0
| * | | riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng2019-09-173-3/+0Star
| * | | riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng2019-09-173-9/+13
| * | | riscv: hw: Change create_fdt() to return voidBin Meng2019-09-172-14/+8Star
| * | | riscv: hw: Remove not needed PLIC properties in device treeBin Meng2019-09-172-4/+0Star
| * | | riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2019-09-172-21/+21
| * | | riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-173-8/+0Star
| * | | riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng2019-09-172-2/+0Star
| * | | riscv: sifive_test: Add reset functionalityBin Meng2019-09-172-1/+6
| * | | riscv: hmp: Add a command to show virtual memory mappingsBin Meng2019-09-173-1/+234
| * | | riscv: Resolve full path of the given bios imageBin Meng2019-09-171-3/+3
| * | | riscv: Add a helper routine for finding firmwareBin Meng2019-09-172-7/+16
| * | | riscv: rv32: Root page table address can be larger than 32-bitBin Meng2019-09-171-5/+5
| * | | target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis2019-09-171-17/+18
| * | | target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-173-10/+26
| * | | riscv: plic: Remove unused interrupt functionsAlistair Francis2019-09-172-15/+0Star
| * | | target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2019-09-172-21/+16Star
| * | | target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2019-09-172-5/+2Star
| * | | riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck2019-09-171-1/+1
| * | | riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck2019-09-171-2/+17
| * | | riscv: sifive_u: Add support for loading initrdGuenter Roeck2019-09-171-3/+17
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* | | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2019-09-1712-33/+521
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| * | virtio-mmio: implement modern (v2) personality (virtio-1)Sergio Lopez2019-09-161-23/+319
| * | virtio pmem: user documentPankaj Gupta2019-09-161-0/+75
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