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| * | | target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb flags. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | target/riscv: Fix mstatus dirty maskAlistair Francis2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is meant to mask off the hypervisor bits, but a typo caused it to mask MPP instead. Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits") Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | target/riscv: Use both register name and ABI nameAtish Patra2019-09-171-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use both the generic register name and ABI name for the general purpose registers and floating point registers. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Update model and compatible strings in device treeBin Meng2019-09-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-172-25/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-173-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the GEM support in sifive_u machine is seriously broken. The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using create_unimplemented_device(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the <reg> property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-172-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-173-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: roms: Update default bios for sifive_u machineBin Meng2019-09-172-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the support of heterogeneous harts and PRCI model, it's now possible to use the OpenSBI image (PLATFORM=sifive/fu540) built for the real hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Change UART node name in device treeBin Meng2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will use this information to locate the serial node and probe its driver. However currently we generate the UART node name as "/soc/uart@...", causing U-Boot fail to find the serial node in DT. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-172-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-172-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-172-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-172-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive: Implement PRCI model for FU540Bin Meng2019-09-173-0/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng2019-09-171-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-172-26/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-172-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not useful if we only have one management CPU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Set default CPUs to 2] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2019-09-172-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hart: Extract hart realize to a separate routineBin Meng2019-09-171-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng2019-09-173-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2019-09-172-15/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use create_unimplemented_device() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2019-09-172-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and SIFIVE_E_PRCI_HFXOSCCFG_EN should be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng2019-09-175-114/+111Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng2019-09-171-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: roms: Remove executable attribute of opensbi imagesBin Meng2019-09-173-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like other binary files, the executable attribute of opensbi images should not be set. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng2019-09-173-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The inclusion of "target/riscv/cpu.h" is unnecessary in various sifive model drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng2019-09-173-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...) in various sifive models. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Change create_fdt() to return voidBin Meng2019-09-172-14/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Remove not needed PLIC properties in device treeBin Meng2019-09-172-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2019-09-172-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-173-8/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "linux,phandle" property is optional. Remove all instances in the sifive_u, virt and spike machine device trees. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng2019-09-172-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly added "hw/hw.h" to sifive_prci.c and sifive_test.c. Another inclusion of "hw/hw.h" was later added via commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that resulted in duplicated inclusion of "hw/hw.h". Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_test: Add reset functionalityBin Meng2019-09-172-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: hmp: Add a command to show virtual memory mappingsBin Meng2019-09-173-1/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds 'info mem' command for RISC-V, to show virtual memory mappings that aids debugging. Rather than showing every valid PTE, the command compacts the output by merging all contiguous physical address mappings into one block and only shows the merged block mapping details. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: Resolve full path of the given bios imageBin Meng2019-09-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present when "-bios image" is supplied, we just use the straight path without searching for the configured data directories. Like "-bios default", we add the same logic so that "-L" actually works. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: Add a helper routine for finding firmwareBin Meng2019-09-172-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: rv32: Root page table address can be larger than 32-bitBin Meng2019-09-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For RV32, the root page table's PPN has 22 bits hence its address bits could be larger than the maximum bits that target_ulong is able to represent. Use hwaddr instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis2019-09-171-17/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the Hypervisor CSR addresses to match the v0.4 spec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-173-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's create a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Christophe de Dinechin <dinechin@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: plic: Remove unused interrupt functionsAlistair Francis2019-09-172-15/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2019-09-172-21/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the always-compiled trace events, remove the now unused RISCV_DEBUG_PMP definition. Note pmpaddr_csr_read() could previously do out-of-bound accesses passing addr_index >= MAX_RISCV_PMPS. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2019-09-172-5/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RISC-V Physical Memory Protection is restricted to privileged modes. Restrict its compilation to QEMU system builds. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The correct property name is clock-names, not clocks-names. Without this patch, the Ethernet driver fails to instantiate with the following error. macb 100900fc.ethernet: failed to get macb_clk (-2) macb: probe of 100900fc.ethernet failed with error -2 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck2019-09-171-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The riscv uart needs valid clocks. This requires a refereence to the clock node. Since the SOC clock is not emulated by qemu, add a reference to a fixed clock instead. The clock-frequency entry in the uart node does not seem to be necessary, so drop it. In addition to a reference to the clock, the driver also needs an aliases entry for the serial node. Add it as well. Without this patch, the serial driver fails to instantiate with the following error message. sifive-serial 10013000.uart: unable to find controller clock sifive-serial: probe of 10013000.uart failed with error -2 when trying to boot Linux. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | | riscv: sifive_u: Add support for loading initrdGuenter Roeck2019-09-171-3/+17
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for loading initrd with "-initrd <filename>" to the sifive_u machine. This lets us boot into Linux without disk drive. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* | | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2019-09-1712-33/+521
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio,vhost,pc: features, fixes, cleanups. Virtio 1.0 support for virtio-mmio. Misc fixes, cleanups. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 16 Sep 2019 16:17:30 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-mmio: implement modern (v2) personality (virtio-1) virtio pmem: user document intel_iommu: Remove the caching-mode check during flag change pc/q35: Disallow vfio-pci hotplug without VT-d caching mode qdev/machine: Introduce hotplug_allowed hook intel_iommu: Sanity check vfio-pci config on machine init done backends/vhost-user.c: prevent using uninitialized vqs vhost-user-blk: prevent using uninitialized vqs docs/nvdimm: add example on persistent backend setup MAINTAINERS: update virtio-rng and virtio-serial maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | virtio-mmio: implement modern (v2) personality (virtio-1)Sergio Lopez2019-09-161-23/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the modern (v2) personality, according to the VirtIO 1.0 specification. Support for v2 among guests is not as widespread as it'd be desirable. While the Linux driver has had it for a while, support is missing, at least, from Tianocore EDK II, NetBSD and FreeBSD. For this reason, the v2 personality is disabled, keeping the legacy behavior as default. Machine types willing to use v2, can enable it using MachineClass's compat_props. Signed-off-by: Sergio Lopez <slp@redhat.com> Message-Id: <20190913120559.40835-1-slp@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * | virtio pmem: user documentPankaj Gupta2019-09-161-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch documents the steps to use virtio pmem. It also documents other useful information about virtio pmem e.g use-case, comparison with Qemu NVDIMM backend and current limitations. Signed-off-by: Pankaj Gupta <pagupta@redhat.com> Message-Id: <20190821121624.5382-1-pagupta@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-04 13:32:30 +0100