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* hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPUPeter Maydell2017-01-202-3/+13
* target-arm: Expose output GPIO line for VCPU maintenance interruptPeter Maydell2017-01-202-0/+5
* hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQPeter Maydell2017-01-202-0/+8
* hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQPeter Maydell2017-01-202-0/+8
* hw/arm/virt-acpi - reserve ECAM space as PNP0C02 deviceArd Biesheuvel2017-01-201-0/+7
* arm: virt: Fix segmentation fault when specifying an unsupported CPUShannon Zhao2017-01-201-1/+0Star
* aspeed: use first FMC flash as a boot ROMCédric Le Goater2017-01-201-0/+41
* aspeed/smc: extend tests for Command modeCédric Le Goater2017-01-201-0/+102
* aspeed/smc: reset flash after each testCédric Le Goater2017-01-201-0/+31
* aspeed/smc: handle SPI flash Command modeCédric Le Goater2017-01-202-26/+131
* aspeed/smc: adjust the size of the register regionCédric Le Goater2017-01-202-15/+11Star
* aspeed/smc: unfold the AspeedSMCController arrayCédric Le Goater2017-01-202-18/+74
* aspeed/smc: autostrap CE0/1 configurationCédric Le Goater2017-01-201-5/+27
* aspeed/smc: rework the prototype of the AspeedSMCFlash helper routinesCédric Le Goater2017-01-201-17/+22
* aspeed/smc: remove call to aspeed_smc_update_cs() in reset functionCédric Le Goater2017-01-201-2/+1Star
* aspeed/smc: remove call to reset in realize functionCédric Le Goater2017-01-201-2/+0Star
* target/arm: Implement DBGVCR32_EL2 system registerPeter Maydell2017-01-201-0/+7
* target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()Peter Maydell2017-01-201-0/+14
* block: m25p80: Improve 1GiB Micron flash definitionMarcin Krzeminski2017-01-201-2/+4
* block: m25p80: Introduce die erase commandMarcin Krzeminski2017-01-201-1/+40
* block: m25p80: Add Quad Page Program 4byteMarcin Krzeminski2017-01-201-0/+4
* arm: Uniquely name imx25 I2C buses.Alastair D'Silva2017-01-202-2/+2
* Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into s...Peter Maydell2017-01-1922-528/+1227
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| * target-sparc: fix up niagara machineArtyom Tarasenko2017-01-186-39/+199
| * target-sparc: move common cpu initialisation routines to sparc64.cArtyom Tarasenko2017-01-185-345/+389
| * target-sparc: implement sun4v RTCArtyom Tarasenko2017-01-184-0/+111
| * target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko2017-01-181-0/+11
| * target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2017-01-182-8/+47
| * target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko2017-01-181-0/+31
| * target-sparc: add more registers to dump_mmuArtyom Tarasenko2017-01-181-0/+2
| * target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko2017-01-181-0/+22
| * target-sparc: allow 256M sized pagesArtyom Tarasenko2017-01-181-17/+1Star
| * target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko2017-01-181-36/+15Star
| * target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2017-01-182-22/+104
| * target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko2017-01-184-37/+25Star
| * target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko2017-01-181-2/+4
| * target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko2017-01-181-0/+1
| * target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko2017-01-181-14/+18
| * target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2017-01-182-5/+4Star
| * target-sparc: fix immediate UA2005 trapsArtyom Tarasenko2017-01-181-1/+1
| * target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko2017-01-181-2/+5
| * target-sparc: implement UA2005 GL registerArtyom Tarasenko2017-01-186-7/+58
| * target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko2017-01-183-5/+39
| * target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2017-01-182-3/+7
| * target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko2017-01-181-0/+11
| * target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko2017-01-183-0/+26
| * target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko2017-01-181-3/+2Star
| * target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko2017-01-181-1/+2
| * target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko2017-01-181-0/+4
| * target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko2017-01-181-0/+17
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