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bwlp/qemu.git
block_qcow2_cluster_info
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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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Author
Age
Files
Lines
*
bsd-user: Add stubs for new signal routines
Warner Losh
2021-11-03
1
-0
/
+21
*
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Richard Henderson
2021-11-03
24
-109
/
+239
|
\
|
*
hw/i386: fix vmmouse registration
Pavel Dovgalyuk
2021-11-02
1
-0
/
+1
|
*
pci: Export pci_for_each_device_under_bus*()
Peter Xu
2021-11-02
9
-29
/
+27
|
*
pci: Define pci_bus_dev_fn/pci_bus_fn/pci_bus_ret_fn
Peter Xu
2021-11-02
2
-24
/
+15
|
*
hw/i386/pc: Allow instantiating a virtio-iommu device
Jean-Philippe Brucker
2021-11-01
3
-2
/
+25
|
*
hw/i386/pc: Move IOMMU singleton into PCMachineState
Jean-Philippe Brucker
2021-11-01
3
-19
/
+20
|
*
hw/i386/pc: Remove x86_iommu_get_type()
Jean-Philippe Brucker
2021-11-01
6
-38
/
+9
|
*
hw/acpi: Add VIOT table
Jean-Philippe Brucker
2021-11-01
4
-0
/
+132
|
*
vhost-vdpa: Set discarding of RAM broken when initializing the backend
David Hildenbrand
2021-11-01
1
-0
/
+13
|
*
qtest: fix 'expression is always false' build failure in qtest_has_accel()
Igor Mammedov
2021-11-01
1
-1
/
+1
*
|
Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging
Richard Henderson
2021-11-02
9
-2106
/
+897
|
\
\
|
*
|
Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"
Philippe Mathieu-Daudé
2021-11-02
1
-2
/
+0
|
*
|
hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
BALATON Zoltan
2021-11-02
1
-0
/
+13
|
*
|
usb/uhci: Replace pci_set_irq with qemu_set_irq
BALATON Zoltan
2021-11-02
2
-2
/
+4
|
*
|
usb/uhci: Disallow user creating a vt82c686-uhci-pci device
BALATON Zoltan
2021-11-02
3
-0
/
+6
|
*
|
usb/uhci: Misc clean up
BALATON Zoltan
2021-11-02
1
-5
/
+2
|
*
|
target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+0
|
*
|
target/mips: Fix Loongson-3A4000 MSAIR config register
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+1
|
*
|
target/mips: Remove one MSA unnecessary decodetree overlap group
Philippe Mathieu-Daudé
2021-11-02
1
-182
/
+180
|
*
|
target/mips: Remove generic MSA opcode
Philippe Mathieu-Daudé
2021-11-02
2
-9
/
+0
|
*
|
target/mips: Convert CTCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-58
/
+16
|
*
|
target/mips: Convert CFCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-9
/
+23
|
*
|
target/mips: Convert MSA MOVE.V opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-6
/
+20
|
*
|
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-88
/
+19
|
*
|
target/mips: Convert MSA COPY_U opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-26
/
+41
|
*
|
target/mips: Convert MSA ELM instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-13
/
+52
|
*
|
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Philippe Mathieu-Daudé
2021-11-02
2
-863
/
+106
|
*
|
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Philippe Mathieu-Daudé
2021-11-02
2
-34
/
+9
|
*
|
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Philippe Mathieu-Daudé
2021-11-02
2
-158
/
+35
|
*
|
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Philippe Mathieu-Daudé
2021-11-02
2
-12
/
+11
|
*
|
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Philippe Mathieu-Daudé
2021-11-02
2
-176
/
+76
|
*
|
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Philippe Mathieu-Daudé
2021-11-02
2
-39
/
+38
|
*
|
target/mips: Convert MSA VEC instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-75
/
+31
|
*
|
target/mips: Convert MSA 2R instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-75
/
+19
|
*
|
target/mips: Convert MSA FILL opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-12
/
+21
|
*
|
target/mips: Convert MSA 2RF instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-85
/
+53
|
*
|
target/mips: Convert MSA load/store instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-59
/
+36
|
*
|
target/mips: Convert MSA I8 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-56
/
+27
|
*
|
target/mips: Convert MSA SHF opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-17
/
+22
|
*
|
target/mips: Convert MSA BIT instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-97
/
+101
|
*
|
target/mips: Convert MSA I5 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-77
/
+41
|
*
|
target/mips: Convert MSA LDI opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-9
/
+21
|
*
|
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
Philippe Mathieu-Daudé
2021-11-02
2
-18
/
+17
|
*
|
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
Philippe Mathieu-Daudé
2021-11-02
1
-3
/
+3
|
*
|
target/mips: Have check_msa_access() return a boolean
Philippe Mathieu-Daudé
2021-11-02
1
-7
/
+18
|
*
|
target/mips: Use dup_const() to simplify
Philippe Mathieu-Daudé
2021-11-02
1
-20
/
+3
|
*
|
target/mips: Adjust style in msa_translate_init()
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+3
|
*
|
target/mips: Fix MSA MSUBV.B opcode
Philippe Mathieu-Daudé
2021-11-02
1
-16
/
+16
|
*
|
target/mips: Fix MSA MADDV.B opcode
Philippe Mathieu-Daudé
2021-11-02
1
-16
/
+16
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