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* tcg: Make CPUClass.debug_excp_handler optionalEduardo Habkost2020-12-161-1/+3
* tcg: make CPUClass.cpu_exec_* optionalEduardo Habkost2020-12-161-3/+8
* tcg: cpu_exec_{enter,exit} helpersEduardo Habkost2020-12-161-5/+18
* accel/tcg: Remove special case for GCC < 4.6Philippe Mathieu-Daudé2020-12-151-1/+1
* icount: improve exec nocache usagePavel Dovgalyuk2020-12-151-1/+1
* accel/tcg: Remove deprecated '-tb-size' optionPhilippe Mathieu-Daudé2020-12-151-1/+1
* accel/tcg: rename tcg-cpus functions to match module nameClaudio Fontana2020-12-117-64/+64
* accel/tcg: split tcg_start_vcpu_threadClaudio Fontana2020-12-118-87/+71Star
* accel/tcg: split CpusAccel into three TCG variantsClaudio Fontana2020-12-1110-461/+645
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20201027' into...Peter Maydell2020-10-301-0/+4
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| * accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile()Peter Maydell2020-10-271-0/+4
* | spapr: Unrealize vCPUs with qdev_unrealize()Greg Kurz2020-10-271-0/+4
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* accel/tcg: Add tlb_flush_page_bits_by_mmuidx*Richard Henderson2020-10-201-9/+266
* accel/tcg: Fix computing of is_write for MIPSKele Huang2020-10-081-4/+39
* gdbstub: add reverse step support in replay modePavel Dovgalyuk2020-10-061-0/+1
* replay: don't record interrupt pollPavel Dovgalyuk2020-10-061-3/+18
* accel/tcg: use current_machine as it is always set for softmmuClaudio Fontana2020-10-051-10/+1Star
* cpus: add handle_interrupt to the CpusAccel interfaceClaudio Fontana2020-10-052-26/+28
* cpus: extract out TCG-specific code to accel/tcgClaudio Fontana2020-10-054-6/+575
* icount: rename functions to be consistent with the module nameClaudio Fontana2020-10-051-3/+3
* cpu-timers, icount: new modulesClaudio Fontana2020-10-053-9/+40
* disas: Move host asm annotations to tb_gen_codeRichard Henderson2020-10-031-9/+15
* exec: Remove MemoryRegion::global_locking fieldPhilippe Mathieu-Daudé2020-09-301-2/+2
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-235-57/+59
* qemu/: fix some comment spelling errorszhaolichang2020-09-171-1/+1
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-2/+2
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-2/+3
* configure: move -ldl test to mesonPaolo Bonzini2020-09-081-1/+1
* cputlb: Make store_helper less fragile to compiler optimizationsRichard Henderson2020-09-031-59/+79
* meson: accelMarc-André Lureau2020-08-212-9/+15
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-213-2/+2
* trace: switch position of headers to what Meson requiresPaolo Bonzini2020-08-213-2/+3
* accel/tcg: better handle memory constrained systemsAlex Bennée2020-07-271-1/+6
* tcg: update comments for save_iotlb_data in cputlbAlex Bennée2020-07-241-6/+5Star
* tcg/cpu-exec: precise single-stepping after an interruptRichard Henderson2020-07-171-1/+7
* tcg/cpu-exec: precise single-stepping after an exceptionLuc Michel2020-07-161-0/+11
* cputlb: ensure we save the IOTLB data in case of resetAlex Bennée2020-07-151-3/+35
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-101-3/+1Star
* qapi: Use returned bool to check for failure, Coccinelle partMarkus Armbruster2020-07-101-2/+1Star
* osdep: Make MIN/MAX evaluate arguments only onceEric Blake2020-06-261-3/+3
* translate-all: call qemu_spin_destroy for PageDescEmilio G. Cota2020-06-161-0/+9
* tcg: call qemu_spin_destroy for tb->jmp_lockEmilio G. Cota2020-06-161-0/+8
* cputlb: destroy CPUTLB with tlb_destroyEmilio G. Cota2020-06-161-0/+15
* accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handlerNick Hudson2020-06-021-0/+27
* accel/tcg: Adjust cpu_signal_handler for NetBSD/armNick Hudson2020-06-021-3/+13
* tcg: Implement gvec support for rotate by vectorRichard Henderson2020-06-022-0/+106
* tcg: Implement gvec support for rotate by immediateRichard Henderson2020-06-022-0/+53
* translate-all: include guest address in out_asm outputAlex Bennée2020-05-151-6/+33
* disas: include an optional note for the start of disassemblyAlex Bennée2020-05-151-2/+2
* accel/tcg: don't disable exec_tb trace eventsAlex Bennée2020-05-151-4/+4
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