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* tcg: Fix LGPL version numberThomas Huth2019-01-309-9/+9
* accel/tcg: Add cluster number to TCG TB hashPeter Maydell2019-01-292-0/+6
* accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs writePeter Maydell2019-01-291-14/+52
* cputlb: Remove static tlb sizingRichard Henderson2019-01-281-21/+0Star
* tcg: introduce dynamic TLB sizingEmilio G. Cota2019-01-281-5/+197
* cputlb: do not evict empty entries to the vtlbEmilio G. Cota2019-01-281-1/+10
* tcg: Add opcodes for vector minmax arithmeticRichard Henderson2019-01-282-0/+244
* tcg: Add gvec expanders for nand, nor, eqvRichard Henderson2019-01-282-0/+36
* qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini2019-01-111-2/+2
* build-sys: don't include windows.h, osdep.h does itMarc-André Lureau2019-01-111-4/+0Star
* accel: Improve selection of the default acceleratorThomas Huth2019-01-111-3/+15
* hw: apply accel compat properties without touching globalsMarc-André Lureau2019-01-071-12/+0Star
* tcg: Add RISC-V cpu signal handlerAlistair Francis2018-12-251-0/+75
* accel: register global_props like machine globalsMarc-André Lureau2018-12-111-1/+8
* cputlb: Remove tlb_c.pending_flushesRichard Henderson2018-10-311-14/+2Star
* cputlb: Filter flushes on already clean tlbsRichard Henderson2018-10-311-10/+25
* cputlb: Count "partial" and "elided" tlb flushesRichard Henderson2018-10-312-7/+19
* cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidxRichard Henderson2018-10-311-46/+12Star
* cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_workRichard Henderson2018-10-311-72/+21Star
* cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson2018-10-311-3/+2Star
* cputlb: Split large page tracking per mmu_idxRichard Henderson2018-10-311-77/+61Star
* cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson2018-10-311-12/+23
* cputlb: Remove tcg_enabled hack from tlb_flush_nocheckRichard Henderson2018-10-311-7/+0Star
* cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson2018-10-311-24/+24
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2018-10-191-3/+53
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| * target-i386 : add coalesced_pio APIPeng Hao2018-10-191-3/+53
* | cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota2018-10-192-12/+19
* | tcg: Split CONFIG_ATOMIC128Richard Henderson2018-10-193-7/+21
* | tcg: Add tlb_index and tlb_entry helpersRichard Henderson2018-10-192-63/+61Star
* | cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota2018-10-191-71/+84
* | cputlb: fix assert_cpu_is_self macroEmilio G. Cota2018-10-191-2/+2
* | exec: introduce tlb_initEmilio G. Cota2018-10-191-0/+4
* | tcg: access cpu->icount_decr.u16.high with atomicsEmilio G. Cota2018-10-192-2/+2
* | tcg: Implement CPU_LOG_TB_NOCHAIN during expansionRichard Henderson2018-10-191-1/+1
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* accel/tcg: Remove dead codeThomas Huth2018-10-021-9/+0Star
* translator: fix breakpoint processingPavel Dovgalyuk2018-10-021-2/+6
* qht: drop ht argument from qht iteratorsEmilio G. Cota2018-09-261-4/+2Star
* KVM: cleanup unnecessary #ifdef KVM_CAP_...Paolo Bonzini2018-08-231-2/+0Star
* kvm: Use inhibit to prevent ballooning without synchronous mmuAlex Williamson2018-08-171-0/+4
* accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell2018-08-141-21/+8Star
* accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code()Peter Maydell2018-08-141-85/+10Star
* accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAMPeter Maydell2018-08-141-1/+18
* accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint()Peter Maydell2018-08-141-1/+3
* accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookupsPeter Maydell2018-08-141-0/+3
* accel/tcg: Pass read access type through to io_readx()Peter Maydell2018-08-142-6/+10
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2018-07-171-1/+1
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| * accel: Fix typo and grammar in commentStefan Weil2018-07-161-1/+1
* | accel/tcg: Assert that tlb fill gave us a valid TLB entryPeter Maydell2018-07-161-2/+2
* | accel/tcg: Use correct test when looking in victim TLB for codePeter Maydell2018-07-161-1/+1
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* translate-all: honour CF_NOCACHE in tb_gen_codeEmilio G. Cota2018-07-091-15/+19
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