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* Preliminary BSD user emulator supportblueswir12008-10-261-0/+16
* CRIS: Fix brk 8 and add S-flag emulation.edgar_igl2008-10-081-1/+1
* SH4: Privilege check for instructionsaurel322008-09-151-1/+4
* Support for address maskingblueswir12008-07-171-2/+3
* Fix r4641 (invalid token "=<" in a preprocessor expression)blueswir12008-07-081-1/+1
* Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.ths2008-07-031-3/+3
* Spelling fixes, spotted by Stuart Brady.ths2008-06-301-1/+1
* Add instruction counter.pbrook2008-06-291-30/+63
* More efficient target register / TC accesses.ths2008-06-271-1/+1
* CRIS: Emulate NMIs.edgar_igl2008-06-101-1/+9
* Multithreaded locking fixes.pbrook2008-06-071-14/+11Star
* CRIS: Add the P flag to the tb dependent flags.edgar_igl2008-06-061-1/+1
* reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworke...bellard2008-06-041-44/+45
* Restore ARM signal handler compilation on glibc < 2.5 (Blue Swirl).balrog2008-06-021-0/+4
* Remove unused (for now) reg_REGWPTR (original patch by Glauber Costa)blueswir12008-05-291-13/+0Star
* SVM reworkbellard2008-05-281-1/+0Star
* removed unused codebellard2008-05-271-7/+0Star
* CRIS: Re-add the X flag to the tb flags, it allows for better code generation...edgar_igl2008-05-271-1/+1
* Move non-op functions from op_helper.c to helper.c and vice versa.blueswir12008-05-271-2/+3
* Fix Sparc32 compilation broken by r4484blueswir12008-05-191-1/+1
* Fix Sparc64 host signal handlingblueswir12008-05-181-5/+10
* Improved workaround for the annoying glibc global register mangling bugblueswir12008-05-171-47/+11Star
* Always process real timers regardless of singlestep mode (Jason Wessel).edgar_igl2008-05-151-1/+1
* Fix compilation on Sparc host, implement ld and stblueswir12008-05-141-5/+0Star
* CRIS: Improve TLB management and handle delayslots at page boundaries.edgar_igl2008-05-131-0/+1
* use new helper namebellard2008-05-131-1/+1
* the double/triple fault handling was not tested in user mode.bellard2008-05-121-0/+2
* initial global prologue/epilogue implementationbellard2008-05-101-62/+3Star
* Fix compiler warnings in common filesblueswir12008-05-101-1/+1
* Debugger single step without interrupts (Jason Wessel).edgar_igl2008-05-091-1/+1
* CRIS: Remove X flag from tb flags.edgar_igl2008-05-071-1/+1
* Fix signal handler compilation on __arm__.balrog2008-05-061-1/+1
* Fix crash due to invalid env->current_tb (Adam Lackorzynski, Paul Brook, me)blueswir12008-05-041-24/+44
* CRIS: Reduce the number of tb dependent flags.edgar_igl2008-05-031-1/+1
* CRIS updates:edgar_igl2008-05-031-1/+1
* x86: Introduce CPU_INTERRUPT_NMIaurel322008-04-131-0/+6
* HPPA (PA-RISC) host supportaurel322008-04-121-0/+29
* Fix compiler warningsaurel322008-04-111-0/+4
* * Add a model of the ETRAX interrupt controller.edgar_igl2008-03-141-5/+0Star
* reverted -translation option supportbellard2008-02-011-62/+1Star
* use the TCG code generatorbellard2008-02-011-2/+2
* Add option to disable TB cache, by Herve Poussineau.ths2008-01-231-1/+61
* Partial fix to Sparc32 Linux host global register mangling problemblueswir12007-12-111-22/+52
* Fix code generation buffer overflow reported by TeLeManblueswir12007-12-111-1/+1
* SH4: system emulator interrupt update, by Magnus Damm.ths2007-12-021-1/+4
* SH4 delay slot code update, by Magnus Damm.ths2007-12-021-2/+2
* Fix TB chaining for exceptions.pbrook2007-11-231-35/+17Star
* consistent types for cpu_x86_fsave and cpu_x86_frstorbellard2007-11-111-4/+4
* removed warningbellard2007-11-111-2/+2
* ARMv7 support.pbrook2007-11-111-1/+12
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