| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target-mips: add MTHC0 and MFHC0 instructions | Leon Alrae | 2015-06-12 | 1 | -0/+2 |
| * | target-mips: add ERETNC instruction and Config5.LLB bit | Leon Alrae | 2015-06-11 | 1 | -0/+1 |
| * | disas/mips: disable unused mips16_to_32_reg_map[] | Leon Alrae | 2014-12-16 | 1 | -1/+2 |
| * | disas/mips: remove unused mips_msa_control_names_numeric[32] | Leon Alrae | 2014-12-16 | 1 | -7/+0 |
| * | disas/mips.c: disassemble MSA instructions | Yongbok Kim | 2014-11-03 | 1 | -2/+714 |
| * | target-mips: add TLBINV support | Leon Alrae | 2014-11-03 | 1 | -0/+2 |
| * | target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions | Yongbok Kim | 2014-10-14 | 1 | -0/+2 |
| * | target-mips: add new Floating Point Comparison instructions | Yongbok Kim | 2014-10-14 | 1 | -0/+44 |
| * | target-mips: add new Floating Point instructions | Leon Alrae | 2014-10-14 | 1 | -0/+22 |
| * | target-mips: add AUI, LSA and PCREL instruction families | Leon Alrae | 2014-10-14 | 1 | -3/+39 |
| * | target-mips: add compact and CP1 branches | Yongbok Kim | 2014-10-13 | 1 | -3/+64 |
| * | target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions | Yongbok Kim | 2014-10-13 | 1 | -0/+4 |
| * | target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 | Leon Alrae | 2014-10-13 | 1 | -0/+5 |
| * | target-mips: redefine Integer Multiply and Divide instructions | Leon Alrae | 2014-10-13 | 1 | -0/+16 |
| * | target-mips: move PREF, CACHE, LLD and SCD instructions | Leon Alrae | 2014-10-13 | 1 | -0/+4 |
| * | target-mips: move LL and SC instructions | Leon Alrae | 2014-10-13 | 1 | -1/+8 |
| * | target-mips: add SELEQZ and SELNEZ instructions | Leon Alrae | 2014-10-13 | 1 | -0/+8 |
| * | build: kill libdis, move disassemblers to disas/ | Paolo Bonzini | 2012-12-19 | 1 | -0/+4873 |
