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path: root/hw/arm/xlnx-versal.c
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* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-16/+14Star
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-151-1/+1
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3Markus Armbruster2020-06-151-3/+3
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2020-06-151-21/+15Star
* sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster2020-06-151-1/+1
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-151-3/+2Star
* qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster2020-06-151-2/+2
* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-151-1/+1
* hw/arm: versal: Add support for the RTCEdgar E. Iglesias2020-05-041-0/+21
* hw/arm: versal: Add support for SDEdgar E. Iglesias2020-05-041-0/+31
* hw/arm: versal: Embed the APUs into the SoC typeEdgar E. Iglesias2020-05-041-14/+5Star
* hw/arm: versal: Embed the ADMAs into the SoC typeEdgar E. Iglesias2020-05-041-7/+7
* hw/arm: versal: Embed the GEMs into the SoC typeEdgar E. Iglesias2020-05-041-7/+8
* hw/arm: versal: Embed the UARTs into the SoC typeEdgar E. Iglesias2020-05-041-6/+6
* hw/arm: versal: Move misplaced commentEdgar E. Iglesias2020-05-041-1/+1
* hw/arm: versal: Remove inclusion of arm_gicv3_common.hEdgar E. Iglesias2020-05-041-1/+0Star
* hw/arm: versal: Setup the ADMA with 128bit bus-widthEdgar E. Iglesias2020-04-301-0/+2
* hw/arm: versal: Add support for the LPD ADMAsEdgar E. Iglesias2020-03-051-0/+24
* hw/arm: Use TYPE_PL011 to create serial portGavin Shan2020-02-281-1/+2
* qdev: set properties with device_class_set_props()Marc-André Lureau2020-01-241-1/+1
* hw/arm: versal: Add the CRP as unimplementedEdgar E. Iglesias2019-11-261-0/+2
* Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster2019-06-121-1/+1
* arm: Rename hw/arm/arm.h to hw/arm/boot.hPeter Maydell2019-05-231-1/+1
* hw/arm: versal: Add a model of Xilinx Versal SoCEdgar E. Iglesias2018-11-021-0/+323
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