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path: root/hw/intc/arm_gic.c
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* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR registerPhilippe Mathieu-Daudé2021-02-021-1/+1
* hw/intc/arm_gic: Allow to use QTest without crashingPhilippe Mathieu-Daudé2021-02-021-1/+2
* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUsEdgar E. Iglesias2021-01-081-1/+3
* arm_gic: Mask the un-supported priority bitsSai Pavan Boddu2020-02-281-2/+31
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* Include hw/irq.h a lot lessMarkus Armbruster2019-08-161-0/+1
* Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster2019-06-121-0/+1
* hw/intc/arm_gic: Drop GIC_BASE_IRQ macroPeter Maydell2018-09-251-17/+14Star
* hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes largePeter Maydell2018-08-241-1/+1
* intc/arm_gic: Improve tracesLuc Michel2018-08-141-6/+25
* intc/arm_gic: Implement maintenance interrupt generationLuc Michel2018-08-141-0/+97
* intc/arm_gic: Implement gic_update_virt() functionLuc Michel2018-08-141-39/+136
* intc/arm_gic: Implement the virtual interface registersLuc Michel2018-08-141-2/+233
* intc/arm_gic: Wire the vCPU interfaceLuc Michel2018-08-141-2/+35
* intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write)Luc Michel2018-08-141-5/+15
* intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete...Luc Michel2018-08-141-4/+47
* intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irqLuc Michel2018-08-141-19/+33
* intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_p...Luc Michel2018-08-141-12/+38
* intc/arm_gic: Add virtualization enabled IRQ helper functionsLuc Michel2018-08-141-18/+14Star
* intc/arm_gic: Refactor secure/ns access check in the CPU interfaceLuc Michel2018-08-141-17/+22
* intc/arm_gic: Add virtualization extensions helper macros and functionsLuc Michel2018-08-141-0/+5
* intc/arm_gic: Add the virtualization extensions to the GIC stateLuc Michel2018-08-141-1/+1
* intc/arm_gic: Remove some dead code and put some functions staticLuc Michel2018-08-141-21/+2Star
* intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registersLuc Michel2018-08-141-4/+57
* intc/arm_gic: Refactor operations on the distributorLuc Michel2018-08-141-77/+86
* hw/intc/arm_gic: Fix handling of GICD_ITARGETSRPeter Maydell2018-07-161-2/+4
* hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()Peter Maydell2018-07-161-1/+15
* qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé2018-02-051-2/+1Star
* hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1Luc MICHEL2018-01-251-3/+13
* hw/intc/arm_gic: Fix group priority computation for group 1 IRQsLuc MICHEL2018-01-251-1/+2
* hw/intc/arm_gic: Fix C_RPR value on idle priorityLuc MICHEL2018-01-251-0/+5
* hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and ...Luc MICHEL2018-01-251-0/+1
* hw/intc/arm_gic: reserved register addresses are RAZ/WIPeter Maydell2018-01-111-2/+3
* ARM: KVM: Enable in-kernel timers with user space gicAlexander Graf2017-07-111-0/+7
* hw/intc/arm_gic: modernise the DPRINTFAlex Bennée2017-03-091-4/+9
* arm: gic: Remove references to NVICMichael Davidsaver2017-02-281-26/+5Star
* nvic: set pending status for not active interruptsMarcin Krzeminski2016-11-071-2/+20
* hw/intc/gic: RAZ/WI non-sec access to sec interruptsJens Wiklander2016-06-061-6/+62
* hw: explicitly include qemu/log.hPaolo Bonzini2016-05-191-0/+1
* hw/intc/arm_gic: add tracepointsHollis Blanchard2016-05-171-0/+12
* include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster2016-03-221-0/+1
* hw/intc/arm_gic.c: Implement GICv2 GICC_DIRPeter Maydell2016-03-041-1/+44
* arm: Clean up includesPeter Maydell2016-01-291-0/+1
* arm_gic: Update ID registers based on revisionAlistair Francis2016-01-211-5/+30
* hw/arm_gic: Correctly restore nested irq priorityFrançois Baldassari2015-11-191-2/+2
* hw/intc/arm_gic: Remove the definition of NUM_CPUWei Huang2015-11-101-5/+3Star
* maint: remove double semicolons in many filesDaniel P. Berrange2015-09-111-1/+1
* hw/intc/arm_gic: Actually set the active bits for active interruptsPeter Maydell2015-09-081-0/+2
* hw/intc/arm_gic: Drop running_irq and last_active arraysPeter Maydell2015-09-081-29/+74
* hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registersPeter Maydell2015-09-081-2/+112
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