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* Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson2022-05-031-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc cleanups # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmJxKjQcHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5ZD5D/9f5CGbNsrl7kB1t6iS # 1ABr5AeW0g9sidMCsQAe9xhWl6+R2SO/z0bBue+mv1ltG0RSZ1ZXS4FyJFBAhFfR # fZ6J7bvdnawIKOxu5T9NY/UvthdRV0eC8CTo0q6GAJo9MHyIGvo1TOoM2Ld9QpfB # 2uup+9fw3Clh0HSHwV9LSL7v2nucFef4A5P1CJ6d1KHnnej0hfug5o+Aiy+wDLA2 # 5RnTm44dqm9lzTgt/x4MqE6Us7WWQukjlLny8/gyurNTR+6fxLqjsHZG+6woQETu # Gg6angsOoAFyciFZ564rjGv80qQuccMVMjtrKvBZz/cmwUUz+Lb4tU3tUPBqomGX # wiofVtL4qcXs94OHWX654UX/iXgkRqC3r+aC0xT37cL4svC8N69BhilxI5+gIGxZ # ZjaQhHx/0e+Ut3c+xrjYHbywQMd9L9AhRyYSMz5BNeLg9+yUiMR+hvGVR/SubLN1 # iiLS07CRgdOKdP6ts7CC7txAgDw4h3cPN5Hz+gqXMJTcnBKpXpnF1lL+Zd/J5++N # 8qMVQH5O4REQRISsbKaOPW8PCiPESsUaHb/mWkre7iYLgkEdNMVQvRcnfx14ejbk # /KKXolrG1huJXGQGnYvgJArHMBBL+ieIYiT6alKFNRNECLdioL46FuSOlirHVCGe # StU22Vsl61M8ifDOPdolK55X5Q== # =npwd # -----END PGP SIGNATURE----- # gpg: Signature made Tue 03 May 2022 06:12:20 AM PDT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] * tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu: (23 commits) util: rename qemu_*block() socket functions tests: replace qemu_set_nonblock() net: replace qemu_set_nonblock() ui: replace qemu_set_nonblock() hw: replace qemu_set_nonblock() qga: replace qemu_set_nonblock() io: replace qemu_set{_non}block() chardev: replace qemu_set_nonblock() io: make qio_channel_command_new_pid() static Replace fcntl(O_NONBLOCK) with g_unix_set_fd_nonblocking() io: replace pipe() with g_unix_open_pipe(CLOEXEC) virtiofsd: replace pipe() with g_unix_open_pipe(CLOEXEC) os-posix: replace pipe()+cloexec with g_unix_open_pipe(CLOEXEC) tests: replace pipe() with g_unix_open_pipe(CLOEXEC) qga: replace pipe() with g_unix_open_pipe(CLOEXEC) util: replace pipe()+cloexec with g_unix_open_pipe() Replace qemu_pipe() with g_unix_open_pipe() block: move fcntl_setfl() Use g_unix_set_fd_nonblocking() libqtest: split QMP part in libqmp ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Use g_unix_set_fd_nonblocking()Marc-André Lureau2022-05-031-1/+1
| | | | | | | | | | | | | | API available since glib 2.30. It also preserves errno. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* | aspeed/hace: Support AST1030 HACESteven Lee2022-05-031-0/+20
| | | | | | | | | | | | | | | | Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE engine. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | aspeed/hace: Support AST2600 HACESteven Lee2022-05-021-5/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aspeed ast2600 accumulative mode is described in datasheet ast2600v10.pdf section 25.6.4: 1. Allocating and initiating accumulative hash digest write buffer with initial state. * Since QEMU crypto/hash api doesn't provide the API to set initial state of hash library, and the initial state is already set by crypto library (gcrypt/glib/...), so skip this step. 2. Calculating accumulative hash digest. (a) When receiving the last accumulative data, software need to add padding message at the end of the accumulative data. Padding message described in specific of MD5, SHA-1, SHA224, SHA256, SHA512, SHA512/224, SHA512/256. * Since the crypto library (gcrypt/glib) already pad the padding message internally. * This patch is to remove the padding message which fed byguest machine driver. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220426021120.28255-3-steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | aspeed/hace: Support HMAC Key Buffer register.Steven Lee2022-05-021-0/+7
| | | | | | | | | | | | | | | | | | | | Support HACE28: Hash HMAC Key Buffer Base Address Register. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220426021120.28255-2-steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | aspeed/scu: Add AST1030 supportSteven Lee2022-05-021-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | Per ast1030_v07.pdf, AST1030 SOC doesn't have SCU300, the pclk divider selection is defined in SCU310[11:8]. Add a get_apb_freq function and a class init handler for ast1030. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220401083850.15266-7-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | aspeed: sbc: Correct default reset valuesJoel Stanley2022-05-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to correctly report secure boot running firmware, these values must be set. They are taken from a running machine when secure boot is enabled. We don't yet have documentation from ASPEED on what they mean. Set the raw values for now, and in the future improve the model with properties to set these on a per-machine basis. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220310052159.183975-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | hw: aspeed_scu: Introduce clkin_25Mhz attributeSteven Lee2022-05-021-1/+5
| | | | | | | | | | | | | | | | | | | | AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute for aspeed_scu_get_clkin() to return the correct clkin for ast2600. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220315075753.8591-3-steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation functionSteven Lee2022-05-021-1/+38
|/ | | | | | | | | | | | AST2600's HPLL register offset and bit definition are different from AST2500. Add a hpll calculation function and an apb frequency calculation function based on SCU200 register description in ast2600v11.pdf. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: checkpatch fixes ] Message-Id: <20220315075753.8591-2-steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson2022-04-211-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc cleanups # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmJhYIscHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5W0jD/43n8PL2cv42lq6OaIS # OYN9vfW9xgA9THZiUH4xEHYreZh+KofmY1PbJn1n7q+v6DecBiqM4fZr1LY8X3PM # xRUH0l4gjXwYwX2cSSo5UTZ/PF248Uoo3tUE3vgMFkYghHMjKcTtaSkYEPGHf2nR # t3m1qLG9w9YPhVg7PNCntjUKi+w2TtcrRVzP7V7XyFc1HrAoT0ys6KaBBrXMbcjz # SxTRbcwSq+6aPjQIn0RWp8Hp1HkdNjegB98dkyqRLlVaugHZWPYDXDQTgVziQlX8 # dU8YrlvTOtDWwsNP6awWnW6/IjKuJjGR0wT3QKwi8JAZ0YV3egwEKoQRUAyHtnn2 # FkSMYgmJcF0ai1aIJFAx+3PIzCfS49lKXA0t303DtY3hRR9JKGMwaV2do9Wm2irt # o7T1lKKN7R7R8Q3U4OsatYMYm7KYL07NEDiQCPloGvCo27ezkAWCKXAw1mRUkxKF # jKwJPcnOUq21Jp6tpjsR8ifSw70jBSEWQSGqhXnDhZhx2C2/Qqkg2I8DagLiPger # kYxbQ13LTG0R25YHa1r3UmzuD+HpZOM8XoLJc5yun/1UrwyR9ghHrOoxkSnRT2Ks # QFn//xQ2SzUnGBNzNSMfTk8vzludxSWfFnOjkviF6E2Elnw3p8f/kOQRAft5dMBY # ftgoy2yLone3HpKfjuOriicIzg== # =0GLo # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 Apr 2022 06:47:55 AM PDT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] * tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu: (30 commits) qga: use fixed-length and GDateTime for log timestamp tests/fuzz: fix warning qga: remove need for QEMU atomic.h util: replace qemu_get_local_state_pathname() util: use qemu_create() in qemu_write_pidfile() util: use qemu_write_full() in qemu_write_pidfile() util: simplify write in signal handler qtest: simplify socket_send() qga: move qga_get_host_name() Move error_printf_unless_qmp() with monitor unit tests: run-time skip test-qga if TSAN is enabled compiler.h: add QEMU_SANITIZE_{ADDRESS,THREAD} tests: remove block/qdict checks from check-qobject.c include: move qdict_{crumple,flatten} declarations include: add qemu/keyval.h include: move qemu_fdatasync() to osdep include: move qemu_msync() to osdep compiler.h: replace QEMU_NORETURN with G_NORETURN osdep.h: move qemu_build_not_reached() doc/style: CLang -> Clang ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
* | hw/misc: Add a model of the Xilinx Versal CRLEdgar E. Iglesias2022-04-212-0/+422
|/ | | | | | | | | | Add a model of the Xilinx Versal CRL. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0Star
| | | | | | Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw: Fix misleading hexadecimal formatPhilippe Mathieu-Daudé2022-03-241-2/+2
| | | | | | | | | | | | | | "0x%u" format is very misleading, replace by "0x%x". Found running: $ git grep -E '0x%[0-9]*([lL]*|" ?PRI)[dDuU]' hw/ Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20220323114718.58714-3-philippe.mathieu.daude@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* Use g_new() & friends where that makes obvious senseMarkus Armbruster2022-03-213-4/+4
| | | | | | | | | | | | | | | | | | | | | | | g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, it returns T * rather than void *, which lets the compiler catch more type errors. This commit only touches allocations with size arguments of the form sizeof(T). Patch created mechanically with: $ spatch --in-place --sp-file scripts/coccinelle/use-g_new-etc.cocci \ --macro-file scripts/cocci-macro-file.h FILES... Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20220315144156.1595462-4-armbru@redhat.com> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
* hw/misc: Add a model of the Xilinx ZynqMP APU ControlEdgar E. Iglesias2022-03-182-0/+254
| | | | | | | | | Add a model of the Xilinx ZynqMP APU Control. Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc: Add a model of the Xilinx ZynqMP CRFEdgar E. Iglesias2022-03-182-0/+267
| | | | | | | | | | | Add a model of the Xilinx ZynqMP CRF. At the moment this is mostly a stub model. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()Peter Maydell2022-03-181-2/+2
| | | | | | | | | | | | In npcm7xx_clk_sel_init() we allocate a string with g_strdup_printf(). Use g_autofree so we free it rather than leaking it. (Detected with the clang leak sanitizer.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220308170302.2582820-1-peter.maydell@linaro.org
* kvm/msi: do explicit commit when adding msi routesLongpeng(Mike)2022-03-151-1/+4
| | | | | | | | | | | | | | We invoke the kvm_irqchip_commit_routes() for each addition to MSI route table, which is not efficient if we are adding lots of routes in some cases. This patch lets callers invoke the kvm_irqchip_commit_routes(), so the callers can decide how to optimize. [1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg00967.html Signed-off-by: Longpeng <longpeng2@huawei.com> Message-Id: <20220222141116.2091-3-longpeng2@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* macio/pmu.c: remove redundant codeMark Cave-Ayland2022-03-091-33/+0Star
| | | | | | | | | | | Now that the logic related to edge-triggered interrupts is all contained within the mos6522 device the redundant implementation for the mac99 PMU device can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQsMark Cave-Ayland2022-03-092-8/+89
| | | | | | | | | | | | | | | | The mos6522 datasheet describes how the control lines IRQs are edge-triggered according to the configuration in the PCR register. Implement the logic according to the datasheet so that the interrupt bits in IFR are latched when the edge is detected, and cleared when reading portA/portB or writing to IFR as necessary. To maintain bisectibility this change also updates the SCSI, SCSI data, Nubus and VIA2 60Hz/1Hz clocks in the q800 machine to be negative edge-triggered as confirmed by the PCR programming in all of Linux, NetBSD and MacOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mac_via: make SCSI_DATA (DRQ) bit live rather than latchedMark Cave-Ayland2022-03-091-1/+16
| | | | | | | | | | | | | | | | | The VIA2 on the Q800 machine is not a separate chip as in older Macs but instead is integrated into the on-board logic. From analysing the SCSI routines in the MacOS toolbox ROM (and to a lesser extent NetBSD and Linux) the expectation seems to be that the SCSI_DATA (DRQ) bit is live on the Q800 and not latched. Fortunately we can use the recently introduced mos6522 last_irq_levels variable which tracks the edge-triggered state to return the SCSI_DATA (DRQ) bit live to the guest OS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: record last_irq_levels in mos6522_set_irq()Mark Cave-Ayland2022-03-091-2/+9
| | | | | | | | | | | | | To detect edge-triggered IRQs it is necessary to store the last state of each IRQ in a last_irq_levels bitmap. Note: this is a migration break for machines which use mos6522 instances which are g3beige/mac99 (PPC) and q800 (m68k). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: add "info via" HMP command for debuggingMark Cave-Ayland2022-03-091-0/+103
| | | | | | | | | | | | | | | This displays detailed information about the device registers and timers to aid debugging problems with timers and interrupts. Currently the QAPI generators for HumanReadableText don't work correctly if used in qapi/target-misc.json when a non-specified target is built, so for now manually add a hmp_info_via() wrapper until direct support for per-device HMP/QMP commands is implemented. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: add register names to register read/write trace eventsMark Cave-Ayland2022-03-092-5/+12
| | | | | | | | | | | This helps to follow how the guest is programming the mos6522 when debugging. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: use device_class_set_parent_reset() to propagate reset to parentMark Cave-Ayland2022-03-094-5/+9
| | | | | | | | | | | Switch from using a legacy approach to the more formal approach for propagating device reset to the parent. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClassMark Cave-Ayland2022-03-091-9/+0Star
| | | | | | | | | | | Now that the mos6522 IRQs are managed using standard qdev gpios these methods are no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* mos6522: switch over to use qdev gpios for IRQsMark Cave-Ayland2022-03-094-51/+29Star
| | | | | | | | | | | | | | | | For historical reasons each mos6522 instance implements its own setting and update of the IFR flag bits using methods exposed by MOS6522DeviceClass. As of today this is no longer required, and it is now possible to implement the mos6522 IRQs as standard qdev gpios. Switch over to use qdev gpios for the mos6522 device and update all instances accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* hw/misc/pvpanic: Use standard headers insteadzhenwei pi2022-03-063-4/+9
| | | | | | | | | | | | | QEMU side has already imported pvpanic.h from linux, remove bit definitions from include/hw/misc/pvpanic.h, and use include/standard-headers/linux/pvpanic.h instead. Also minor changes for PVPANIC_CRASHLOADED -> PVPANIC_CRASH_LOADED. Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <20220221122717.1371010-2-pizhenwei@bytedance.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' ↵Peter Maydell2022-02-284-0/+148
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * aspeed/sdmc: Add trace eventsCédric Le Goater2022-02-262-0/+6
| | | | | | | | | | | | | | | | This is useful to analyze changes in the U-Boot RAM driver when SDRAM training is performed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ast2600: Add Secure Boot Controller modelJoel Stanley2022-02-262-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | Just a stub that indicates the system has booted in secure boot mode. Used for testing the driver: https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/ Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Fixed typo - Adjusted Copyright dates ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | Mark remaining global TypeInfo instances as constBernhard Beschow2022-02-216-6/+6
|/ | | | | | | | | | | | | | | | | | | More than 1k of TypeInfo instances are already marked as const. Mark the remaining ones, too. This commit was created with: git grep -z -l 'static TypeInfo' -- '*.c' | \ xargs -0 sed -i 's/static TypeInfo/static const TypeInfo/' Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20220117145805.173070-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2022-01-291-1/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/quintela-gitlab/tags/migration-20220128-pull-request' into staging Migration Pull request (Take 2) Hi This time I have disabled vmstate canary patches form Dave Gilbert. Let's see if it works. Later, Juan. # gpg: Signature made Fri 28 Jan 2022 18:30:25 GMT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/quintela-gitlab/tags/migration-20220128-pull-request: (36 commits) migration: Move temp page setup and cleanup into separate functions migration: Simplify unqueue_page() migration: Add postcopy_has_request() migration: Enable UFFD_FEATURE_THREAD_ID even without blocktime feat migration: No off-by-one for pss->page update in host page size migration: Tally pre-copy, downtime and post-copy bytes independently migration: Introduce ram_transferred_add() migration: Don't return for postcopy_send_discard_bm_ram() migration: Drop return code for disgard ram process migration: Do chunk page in postcopy_each_ram_send_discard() migration: Drop postcopy_chunk_hostpages() migration: Don't return for postcopy_chunk_hostpages() migration: Drop dead code of ram_debug_dump_bitmap() migration/ram: clean up unused comment. migration: Report the error returned when save_live_iterate fails migration/migration.c: Remove the MIGRATION_STATUS_ACTIVE when migration finished migration/migration.c: Avoid COLO boot in postcopy migration migration/migration.c: Add missed default error handler for migration state Remove unnecessary minimum_version_id_old fields multifd: Rename pages_used to normal_pages ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Remove unnecessary minimum_version_id_old fieldsPeter Maydell2022-01-281-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The migration code will not look at a VMStateDescription's minimum_version_id_old field unless that VMSD has set the load_state_old field to something non-NULL. (The purpose of minimum_version_id_old is to specify what migration version is needed for the code in the function pointed to by load_state_old to be able to handle it on incoming migration.) We have exactly one VMSD which still has a load_state_old, in the PPC CPU; every other VMSD which sets minimum_version_id_old is doing so unnecessarily. Delete all the unnecessary ones. Commit created with: sed -i '/\.minimum_version_id_old/d' $(git grep -l '\.minimum_version_id_old') with the one legitimate use then hand-edited back in. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> --- It missed vmstate_ppc_cpu.
* | hw/misc: Add a model of Versal's PMC SLCRFrancisco Iglesias2022-01-282-1/+1450
| | | | | | | | | | | | | | | | | | | | | | Add a model of Versal's PMC SLCR (system-level control registers). Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-2-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | rtc: Move RTC function prototypes to their own headerPeter Maydell2022-01-283-3/+3
|/ | | | | | | | | | | | | | | | | softmmu/rtc.c defines two public functions: qemu_get_timedate() and qemu_timedate_diff(). Currently we keep the prototypes for these in qemu-common.h, but most files don't need them. Move them to their own header, a new include/sysemu/rtc.h. Since the C files using these two functions did not need to include qemu-common.h for any other reason, we can remove those include lines when we add the include of the new rtc.h. The license for the .h file follows that of the softmmu/rtc.c where both the functions are defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model.Troy Lee2022-01-203-0/+391
| | | | | | | | | | | | | | | | | | | Aspeed 2600 SDK enables I3C support by default. The I3C driver will try to reset the device controller and set it up through device address table register. This dummy model responds to these registers with default values as listed in the ast2600v10 datasheet chapter 54.2. This avoids a guest machine kernel panic due to referencing an invalid kernel address if the device address table register isn't set correctly. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> Message-id: 20220111084546.4145785-2-troy_lee@aspeedtech.com [PMM: tidied commit message; fixed format strings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* dma: Let dma_memory_read/write() take MemTxAttrs argumentPhilippe Mathieu-Daudé2021-12-302-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Let devices specify transaction attributes when calling dma_memory_read() or dma_memory_write(). Patch created mechanically using spatch with this script: @@ expression E1, E2, E3, E4; @@ ( - dma_memory_read(E1, E2, E3, E4) + dma_memory_read(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) | - dma_memory_write(E1, E2, E3, E4) + dma_memory_write(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) ) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20211223115554.3155328-6-philmd@redhat.com>
* Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into stagingRichard Henderson2021-12-171-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc 7.0 queue: * General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) # gpg: Signature made Fri 17 Dec 2021 09:20:31 AM PST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20211217' of https://github.com/legoater/qemu: (101 commits) ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices ppc/pnv: Move realize of PEC stacks under the PEC model ppc/pnv: Remove "system-memory" property from PHB4 PEC ppc/pnv: Compute the PHB index from the PHB4 PEC model ppc/pnv: Introduce a num_stack class attribute ppc/pnv: Introduce a "chip" property under the PHB4 model ppc/pnv: Introduce version and device_id class atributes for PHB4 devices ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices ppc/pnv: Use QOM hierarchy to scan PHB3 devices ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() ppc/pnv: Drop the "num-phbs" property ppc/pnv: Use the chip class to check the index of PHB3 devices ppc/pnv: Introduce a "chip" property under PHB3 PPC64/TCG: Implement 'rfebb' instruction target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc: enable PMU instruction count target/ppc: enable PMU counter overflow with cycle events target/ppc: PMU: update counters on MMCR1 write target/ppc: PMU: update counters on PMCs r/w target/ppc: PMU basic cycle count for pseries TCG ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * ivshmem.c: change endianness to LITTLE_ENDIANDaniel Henrique Barboza2021-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ivshmem device, as with most PCI devices, uses little endian byte order. However, the endianness of its mmio_ops is marked as DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big endian hosts but also with PowerPC little endian hosts as well, since the Power architecture in QEMU uses big endian hardware (XIVE controller, PCI Host Bridges, etc) even if the host is in little endian byte order. As it is today, the IVPosition of the device will be byte swapped when running in Power BE and LE. This can be seen by changing the existing qtest 'ivshmem-test' to run in ppc64 hosts and printing the IVPOSITION regs in test_ivshmem_server() right after the VM ids assert. For x86_64 the VM id values read are '0' and '1', for ppc64 (tested in a Power8 RHEL 7.9 BE server) and ppc64le (tested in a Power9 RHEL 8.6 LE server) the ids will be '0' and '0x1000000'. Change this device to LITTLE_ENDIAN fixes the issue for Power hosts of both endianness, and every other big-endian architecture that might use this device, without impacting x86 users. Fixes: cb06608e17f8 ("ivshmem: convert to memory API") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/168 Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211124092948.335389-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-151-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. A number of machines connect just one backend with drive_get_next(). Change them to use drive_get() directly. This makes the (zero) unit number explicit in the code. Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Subbaraya Sundeep <sundeep.lkml@gmail.com> Cc: Niek Linnenbank <nieklinnenbank@gmail.com> Cc: Andrew Baumann <Andrew.Baumann@microsoft.com> Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Cc: Jean-Christophe Dubois <jcd@tribudubois.net> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Artyom Tarasenko <atar4qemu@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Laurent Vivier <laurent@vivier.eu> Cc: qemu-arm@nongnu.org Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20211117163409.3587705-3-armbru@redhat.com>
* hw/misc/sifive_u_otp: Do not reset OTP content on hardware resetPhilippe Mathieu-Daudé2021-11-221-8/+5Star
| | | | | | | | | | | | | Once a "One Time Programmable" is programmed, it shouldn't be reset. Do not re-initialize the OTP content in the DeviceReset handler, initialize it once in the DeviceRealize one. Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211119104757.331579-1-f4bug@amsat.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONEThomas Huth2021-11-221-1/+8
| | | | | | | | | | | | | | | | | | Configuring a drive with "if=none" is meant for creation of a backend only, it should not get automatically assigned to a device frontend. Use "if=pflash" for the One-Time-Programmable device instead (like it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). Since the old way of configuring the device has already been published with the previous QEMU versions, we cannot remove this immediately, but have to deprecate it and support it for at least two more releases. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211119102549.217755-1-thuth@redhat.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* pmu: fix pmu vmstate subsection listLaurent Vivier2021-11-171-0/+1
| | | | | | | | | | | | | | | | | | The subsection is not closed by a NULL marker so this can trigger a segfault when the pmu vmstate is saved. This can be easily shown with: $ ./qemu-system-ppc64 -dump-vmstate vmstate.json Segmentation fault (core dumped) Fixes: d811d61fbc6c ("mac_newworld: add PMU device") Cc: mark.cave-ayland@ilande.co.uk Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/m68k: Fix typo in SPDX tagPhilippe Mathieu-Daudé2021-11-091-1/+1
| | | | | | | | | | | | | | | | Fix 'Identifer' -> 'Identifier' typo. Cc: Laurent Vivier <laurent@vivier.eu> Fixes: 8c6df16ff60 ("hw/char: add goldfish-tty") Fixes: 87855593903 ("hw/intc: add goldfish-pic") Fixes: 2fde99ee312 ("m68k: add an interrupt controller") Fixes: 0791bc02b8f ("m68k: add a system controller") Fixes: e1cecdca559 ("m68k: add Virtual M68k Machine") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211103105311.3399293-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* hw/misc: deprecate the 'sga' deviceDaniel P. Berrangé2021-11-021-0/+2
| | | | | | | | | | | This is obsolete since SeaBIOS 1.11.0 introduced native support for sending messages to the serial console. The new support can be activated using -machine graphics=off on x86 targets. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210909123219.862652-1-berrange@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* mac_via: add GPIO for A/UX modeMark Cave-Ayland2021-10-202-0/+20
| | | | | | | | | | Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating whether the hardware is configured for A/UX mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* mac_via: update comment for VIA1B_vMystery bitMark Cave-Ayland2021-10-201-0/+4
| | | | | | | | | | | | According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't particularly descriptive, the patch leaves this to ensure that the constants in mac_via.c remain in sync with Linux's mac_via.h. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Revert "hw/misc: applesmc: use host osk as default on macs"Paolo Bonzini2021-10-131-191/+1Star
| | | | | | | | This reverts commit 93ddefbc3c909bb6c3b76086f1dfc8ad98dd3725. The commit included code under the APSL 2.0, which is incompatible with the GPL v2. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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