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* openrisc: re-randomize rng-seed on rebootJason A. Donenfeld2022-10-271-0/+3
* hw/openrisc: virt: pass random seed to fdtJason A. Donenfeld2022-09-041-0/+6
* hw/openrisc: Initialize timer time at startupStafford Horne2022-09-041-1/+21
* hw/openrisc: Add PCI bus support to virtStafford Horne2022-09-042-6/+157
* hw/openrisc: Add the OpenRISC virtual machineStafford Horne2022-09-043-0/+427
* hw/openrisc: Split re-usable boot time apis out to boot.cStafford Horne2022-09-043-100/+123
* hw/openrisc: use right OMPIC size variableJason A. Donenfeld2022-05-151-2/+2
* hw/openrisc: support 4 serial ports in or1ksimJason A. Donenfeld2022-05-151-6/+16
* hw/openrisc: page-align FDT addressJason A. Donenfeld2022-05-031-1/+1
* hw/openrisc/openrisc_sim: Add support for initrd loadingStafford Horne2022-02-261-0/+31
* hw/openrisc/openrisc_sim: Add automatic device tree generationStafford Horne2022-02-262-16/+175
* hw/openrisc/openrisc_sim: Increase max_cpus to 4Stafford Horne2022-02-251-3/+5
* hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UARTStafford Horne2022-02-251-8/+24
* hw/openrisc/openrisc_sim: Parameterize initializationStafford Horne2022-02-251-8/+34
* hw/openrisc/openrisc_sim: Create machine state for or1ksimStafford Horne2022-02-251-2/+28
* Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
* target/openrisc: Move pic_cpu code into CPU object properPeter Maydell2020-12-153-64/+2Star
* hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"Peter Maydell2020-12-151-17/+21
* hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUsPeter Maydell2020-12-152-2/+12
* meson: convert hw/arch*Marc-André Lureau2020-08-212-2/+5
* sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster2020-06-151-2/+2
* qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster2020-06-151-4/+4
* hw/openrisc/openrisc_sim: Add assertion to silence GCC warningPhilippe Mathieu-Daudé2020-06-101-0/+1
* hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé2020-02-281-1/+1
* hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic2020-01-291-1/+1
* Include hw/qdev-properties.h lessMarkus Armbruster2019-08-161-0/+1
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-163-3/+0Star
* Include migration/vmstate.h lessMarkus Armbruster2019-08-161-0/+1
* Include hw/irq.h a lot lessMarkus Armbruster2019-08-162-0/+2
* Include sysemu/reset.h a lot lessMarkus Armbruster2019-08-161-0/+1
* hw: Replace global smp variables with MachineState for all remaining archsLike Xu2019-07-051-0/+1
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* target/openrisc: Fix LGPL information in the file headersThomas Huth2019-05-083-3/+3
* or1k-softmmu.mak: express dependencies with KconfigPaolo Bonzini2019-03-071-0/+3
* kconfig: introduce kconfig filesPaolo Bonzini2019-03-071-0/+2
* hw/openrisc/Makefile.objs: Create CONFIG_* for openriscYang Zhong2019-02-051-1/+1
* elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick2019-02-051-1/+1
* Change references to serial_hds[] to serial_hd()Peter Maydell2018-04-261-1/+1
* hw/openrisc: Replace fprintf(stderr, "*\n" with error_report()Alistair Francis2018-02-061-2/+2
* openrisc: use generic cpu_model parsingIgor Mammedov2017-10-271-6/+2Star
* openrisc: Only kick cpu on timeout, not on updateStafford Horne2017-10-201-1/+1
* openrisc: Initial SMP supportStafford Horne2017-10-201-23/+65
* openrisc/cputimer: Perparation for MulticoreStafford Horne2017-10-201-15/+47
* cpu: make cpu_generic_init() abort QEMU on errorIgor Mammedov2017-09-191-4/+0Star
* openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov2017-09-011-1/+1
* hw: Use new memory_region_init_{ram, rom, rom_device}() functionsPeter Maydell2017-07-141-2/+1Star
* memory: Rename memory_region_init_ram() to memory_region_init_ram_nomigrate()Peter Maydell2017-07-141-1/+1
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-0/+1
* target/openrisc: Rename the cpu from or32 to or1kRichard Henderson2017-02-131-2/+2
* hw: explicitly include qemu-common.h and cpu.hPaolo Bonzini2016-03-221-0/+2
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