summaryrefslogtreecommitdiffstats
path: root/hw/riscv/Kconfig
Commit message (Expand)AuthorAgeFilesLines
* hw/riscv: Enable TPM backendsAlistair Francis2022-04-291-0/+1
* hw/riscv: virt: Create a platform busAlistair Francis2022-04-291-0/+1
* hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2022-03-031-0/+1
* hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2022-03-031-0/+1
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-201-6/+6
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-201-0/+1
* hw/char: Add config for shakti uartVijai Kumar K2021-09-011-4/+1Star
* hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machinesPhilippe Mathieu-Daudé2021-07-201-0/+5
* hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis2021-05-111-0/+1
* riscv: Add initial support for Shakti C machineVijai Kumar K2021-05-111-0/+10
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-231-0/+1
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-0/+1
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+2
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+1
* hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng2020-09-101-29/+29
* hw/riscv: Drop CONFIG_SIFIVEBin Meng2020-09-101-9/+5Star
* hw/riscv: Always build riscv_hart.cBin Meng2020-09-101-9/+0Star
* hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-101-0/+1
* hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-101-0/+2
* hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-101-3/+0Star
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-0/+5
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-0/+5
* hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-101-0/+2
* hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-101-0/+1
* hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-101-0/+1
* hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-101-0/+1
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-101-0/+1
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-101-0/+1
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-101-0/+1
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-101-0/+1
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-101-0/+6
* hw/char: Initial commit of Ibex UARTAlistair Francis2020-06-191-0/+4
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-031-0/+5
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-101-0/+1
* riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-281-0/+1
* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-171-0/+1
* riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2019-09-171-0/+1
* kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini2019-03-181-0/+1
* riscv/Kconfig: enable PCI_DEVICESDavid Abdurachmanov2019-03-111-0/+3
* riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directivesPaolo Bonzini2019-03-071-0/+13
* kconfig: introduce kconfig filesPaolo Bonzini2019-03-071-0/+20
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-11-21 17:35:06 +0100