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path: root/hw/riscv/microchip_pfsoc.c
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* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-181-0/+21
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+6
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-6/+44
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-1/+10
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-3/+6
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-5/+8
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+18
* hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng2020-11-031-0/+18
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+5
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+14
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+39
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-101-0/+15
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-101-0/+23
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-101-0/+30
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-101-0/+312
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