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path: root/hw/riscv/sifive_u.c
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* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-151-4/+6
* qom: Drop object_property_set_description() parameter @errpMarkus Armbruster2020-05-151-3/+2Star
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-291-1/+1
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-291-0/+4
* riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng2020-04-291-0/+20
* riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis2020-04-291-1/+7
* riscv/sifive_u: Fix up file orderingAlistair Francis2020-04-291-54/+54
* various: Remove suspicious '\' character outside of #define in C codePhilippe Mathieu-Daudé2020-04-291-1/+1
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2020-03-171-1/+1
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| * hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé2020-03-171-1/+1
* | riscv: sifive_u: Update BIOS_FILENAME for 32-bitBin Meng2020-03-171-1/+5
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* hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-1/+1
* riscv/sifive_u: fix a memory leak in soc_realize()Pan Nengyuan2020-01-161-0/+1
* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-1/+2
* riscv/sifive_u: Add the start-in-flash propertyAlistair Francis2019-10-281-1/+29
* riscv/sifive_u: Manually define the machineAlistair Francis2019-10-281-13/+31
* riscv/sifive_u: Add QSPI memory regionAlistair Francis2019-10-281-0/+8
* riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis2019-10-281-0/+16
* riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng2019-10-281-1/+4
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-281-2/+0Star
* riscv: sifive_u: Update model and compatible strings in device treeBin Meng2019-09-171-2/+3
* riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-23/+1Star
* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-171-4/+20
* riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+9
* riscv: sifive_u: Change UART node name in device treeBin Meng2019-09-171-1/+1
* riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2
* riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-171-3/+4
* riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-171-1/+23
* riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-171-0/+23
* riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng2019-09-171-3/+4
* riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-171-25/+67
* riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-171-1/+4
* riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng2019-09-171-1/+0Star
* riscv: hw: Change create_fdt() to return voidBin Meng2019-09-171-7/+4Star
* riscv: hw: Remove not needed PLIC properties in device treeBin Meng2019-09-171-2/+0Star
* riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2019-09-171-9/+9
* riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-171-4/+0Star
* riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck2019-09-171-1/+1
* riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck2019-09-171-2/+17
* riscv: sifive_u: Add support for loading initrdGuenter Roeck2019-09-171-3/+17
* Include sysemu/sysemu.h a lot lessMarkus Armbruster2019-08-161-0/+1
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* hw/riscv: Load OpenSBI as the default firmwareAlistair Francis2019-07-181-3/+4
* hw/riscv: Replace global smp variables with machine smp propertiesLike Xu2019-07-051-4/+7
* hw/riscv: Add support for loading a firmwareAlistair Francis2019-06-271-0/+4
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-15/+2Star
* riscv: sifive_u: Update the plic hart config to support multicoreBin Meng2019-06-271-1/+15
* riscv: sifive_u: Do not create hard-coded phandles in DTBin Meng2019-06-271-7/+10
* riscv: sifive_u: Correct UART0's IRQ in the device treeBin Meng2019-03-191-1/+1
* riscv: sifive_u: Allow up to 4 CPUs to be createdAlistair Francis2019-03-191-1/+4
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