summaryrefslogtreecommitdiffstats
path: root/hw/riscv/sifive_u.c
Commit message (Expand)AuthorAgeFilesLines
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-7/+4Star
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-2/+41
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+52
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-5/+5
* hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng2021-01-161-5/+1Star
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-5/+5
* hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-181-25/+30
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-1/+1
* hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-181-0/+15
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-151-4/+2Star
* hw/riscv: sifive_u: Allow passing custom DTBAnup Patel2020-11-031-8/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-2/+8
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-5/+13
* sifive_u: Register "start-in-flash" as class propertyEduardo Habkost2020-09-221-8/+8
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-78/+78
* hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-101-0/+30
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-0/+2
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-1/+1
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-221-2/+2
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+22
* hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster2020-07-211-0/+1
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-141-1/+1
* RISC-V: Support 64 bit start addressAtish Patra2020-07-141-1/+5
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-141-5/+15
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-15/+13Star
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-141-1/+0Star
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-101-3/+1Star
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-3/+3
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-101-2/+1Star
* riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster2020-07-021-3/+9
* hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-191-0/+4
* hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng2020-06-191-2/+2
* hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-191-8/+31
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-191-3/+3
* hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-191-0/+7
* hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng2020-06-191-6/+8
* hw/riscv: sifive_u: Add reset functionalityBin Meng2020-06-191-1/+23
* hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2020-06-191-2/+41
* hw/riscv: sifive_u: Generate device tree node for OTPBin Meng2020-06-191-0/+11
* hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng2020-06-191-6/+1Star
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-151-6/+3Star
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster2020-06-151-19/+12Star
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-151-9/+3Star
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-8/+6Star
* hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng2020-06-031-12/+12
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 08:52:00 +0100