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path: root/hw/riscv/spike.c
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* hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza2022-10-171-0/+6
* hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza2022-09-071-1/+1
* hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI2022-05-241-1/+1
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng2022-04-291-2/+3
* hw/riscv: Remove macros for ELF BIOS image namesAnup Patel2022-01-211-2/+2
* hw/riscv: spike: Allow using binary firmware as biosAnup Patel2022-01-211-16/+25
* hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2Star
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-201-5/+9
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-201-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0Star
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2Star
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* qtest: delete superfluous inclusions of qtest.hChen Qun2021-03-091-1/+0Star
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-4/+4
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-4/+4
* hw/riscv: spike: Remove compile time XLEN checksAlistair Francis2020-12-181-21/+24
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-1/+2
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-3/+8
* hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-74/+158
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: spike: Change the default bios to use generic platform imageBin Meng2020-08-221-2/+7
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-141-1/+1
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-141-3/+10
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-1/+6
* riscv: Unify Qemu's reset vector code pathAtish Patra2020-07-141-38/+3Star
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2020-06-151-4/+3Star
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-2/+2
* hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis2020-06-031-217/+0Star
* hw/riscv/spike: Allow more than one CPUsAnup Patel2020-04-291-1/+1
* hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel2020-04-291-1/+23
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-291-0/+4
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell2020-03-031-3/+6
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| * hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-3/+6
* | hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé2020-02-281-1/+1
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* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-3/+3
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-281-2/+0Star
* riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng2019-09-171-1/+0Star
* Include sysemu/sysemu.h a lot lessMarkus Armbruster2019-08-161-0/+1
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* hw/riscv: Replace global smp variables with machine smp propertiesLike Xu2019-07-051-0/+3
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-17/+4Star
* riscv: spike: Add a generic spike machineAlistair Francis2019-05-241-1/+105
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